Architecture of the Monitor System in Ternary Optical Computer

2012 ◽  
Vol 616-618 ◽  
pp. 2158-2161
Author(s):  
Xian Chao Wang ◽  
Yun Fei Yao ◽  
Chun Sheng Wang ◽  
Wei Wei Sun ◽  
Kang Zhe Wang
Keyword(s):  
Embedded System ◽  
System Architecture ◽  
Monitor System ◽  
Processor Allocation ◽  
Communication Module ◽  
Optical Computer ◽  
Optical Processor ◽  
The Embedded System ◽  
Data Preprocess ◽  
Ternary Optical Computer

The monitor system architecture in ternary optical computer (TOC) was discussed. There were some important modules, such as the client, network communication module (NCM), data preprocess module (DPM), operation-request scheduling module (ORSM), optical processor allocation module (OPAM) and the embedded system in the architecture. And the communication protocols between these modules were analyzed and designed. At the same time, the functions of the modules were introduced.

scholarly journals Performance Analysis and Evaluation of Ternary Optical Computer Based on Asynchronous Multiple Vacations

2021 ◽  
Author(s):  
Wang Xianchao ◽  
Wang Xianchuan ◽  
Zhang Jie ◽  
Ling Man ◽  
Hou Dayou ◽  
...  
Keyword(s):  
System Performance ◽  
Scheduling Algorithm ◽  
Processor Allocation ◽  
Simulation Experiments ◽  
Analysis And Evaluation ◽  
Task Scheduling Algorithm ◽  
Computer Based ◽  
Optical Computer ◽  
Optical Processor ◽  
Ternary Optical Computer

Abstract Ternary optical computer(TOC) has become a research hotspot in the field because of the advantages such as inherent parallelism, numerous trits, low power consumption, extendibility, bitwise allocability and dynamical bitwise reconfigurability. Meanwhile, its performance evaluation attracts more and more attentions from potential users and researchers. To model its computing ecology more accurately, this paper first builds a three-staged TOC service model by introducing asynchronous multi-vacations and tandem queueing, and then proposes a task scheduling algorithm and an optical processor allocation algorithm with asynchronous vacations of some small optical processors after dividing equally the entire optical processor into several small optical processors which can be used independently. At the same time, the analytical model was established to obtain important performance indicators such as response time, the number of tasks and utilization of optical processor, based on M/M/1 and M/M/n queuing system with asynchronous multi-vacations. In addition, relevant numerical simulation experiments are conducted. The results illustrate that the number of small optical processors, vacation rate and the number of small optical processors allowed to be on vacation have important effects on the system performance. Compared with synchronous vacation, asynchronous vacation not only ensures the system to obtain better maintenance but also improves the system performance to some degree.

A Novel Embedded System Architecture for Fire Detection Based on Image Processing

2014 ◽  
Vol 608-609 ◽  
pp. 454-458
Author(s):  
Wei Bai ◽  
Chen Yuan Hu
Keyword(s):  
Image Processing ◽  
Embedded System ◽  
System Architecture ◽  
Cooperative Control ◽  
Processing System ◽  
Fire Detection ◽  
System Level ◽  
High Definition ◽  
The Embedded System ◽  
Pass Through

This paper presents novel logic/software co-work architecture for embedded high definition image processing platform, which is built by the considerations of system level, board hardware level, and the tasks partition between CPU processing and programmable logic based on the latest launched System on Chip Field Programmable Gate Array (Soc FPGA) – Xilinx ZC7020. For this case, we comprehensive analyze of the critical data paths: the uniform Advanced Extensible Interface (AXI) processing between processing system (PS) and processing logic (PL), including high definition video pass through PL to PS and PS software processing send to PL for speed up. We have included the transplant of opensource Linux, multiprocessing cooperative control and boot loader in PS side. Since the general platform is proposed, a fire detection approach based on high definition image processing is implemented. Experiment results indicated the feasibility and universality of the embedded system architecture.

Processor Allocation of a Ternary Optical Computer

2013 ◽  
Vol 19 (6) ◽  
pp. 1714-1717 ◽  
Author(s):  
Xianchao Wang ◽  
Yunfei Yao ◽  
Chunsheng Wang ◽  
Weiwei Sun ◽  
Kangzhe Wang
Keyword(s):  
Processor Allocation ◽  
Optical Computer ◽  
Ternary Optical Computer

scholarly journals Multiple Narrowband Interferences Characterization, Detection and Mitigation Using Simplified Welch Algorithm and Notch Filtering

2021 ◽  
Vol 11 (3) ◽  
pp. 1331
Author(s):  
Mohammad Hossein Same ◽  
Gabriel Gleeton ◽  
Gabriel Gandubert ◽  
Preslav Ivanov ◽  
Rene Jr Landry
Keyword(s):  
Power Spectrum ◽  
Embedded System ◽  
Radio Frequency ◽  
Satellite Communication ◽  
Signal To Noise Ratio ◽  
Center Frequency ◽  
Infinite Impulse Response ◽  
Frequency Variation ◽  
Welch Method ◽  
The Embedded System

By increasing the demand for radio frequency (RF) and access of hackers and spoofers to low price hardware and software defined radios (SDR), radio frequency interference (RFI) became a more frequent and serious problem. In order to increase the security of satellite communication (Satcom) and guarantee the quality of service (QoS) of end users, it is crucial to detect the RFI in the desired bandwidth and protect the receiver with a proper mitigation mechanism. Digital narrowband signals are so sensitive into the interference and because of their special power spectrum shape, it is hard to detect and eliminate the RFI from their bandwidth. Thus, a proper detector requires a high precision and smooth estimation of input signal power spectral density (PSD). By utilizing the presented power spectrum by the simplified Welch method, this article proposes a solid and effective algorithm that can find all necessary interference parameters in the frequency domain while targeting practical implantation for the embedded system with minimum complexity. The proposed detector can detect several multi narrowband interferences and estimate their center frequency, bandwidth, power, start, and end of each interference individually. To remove multiple interferences, a chain of several infinite impulse response (IIR) notch filters with multiplexers is proposed. To minimize damage to the original signal, the bandwidth of each notch is adjusted in a way that maximizes the received signal to noise ratio (SNR) by the receiver. Multiple carrier wave interferences (MCWI) is utilized as a jamming attack to the Digital Video Broadcasting-Satellite-Second Generation (DVB-S2) receiver and performance of a new detector and mitigation system is investigated and validated in both simulation and practical tests. Based on the obtained results, the proposed detector can detect a weak power interference down to −25 dB and track a hopping frequency interference with center frequency variation speed up to 3 kHz. Bit error ratio (BER) performance shows 3 dB improvement by utilizing new adaptive mitigation scenario compared to non-adaptive one. Finally, the protected DVB-S2 can receive the data with SNR close to the normal situation while it is under the attack of the MCWI jammer.

scholarly journals The Design of a 2D Graphics Accelerator for Embedded Systems

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 469
Author(s):  
Hyun Woo Oh ◽  
Ji Kwang Kim ◽  
Gwan Beom Hwang ◽  
Seung Eun Lee
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Real Time ◽  
Line Drawing ◽  
Cmos Process ◽  
Embedded Processor ◽  
Processor Core ◽  
Field Programmable ◽  
The Embedded System ◽  
Graphics Processing

Recently, advances in technology have enabled embedded systems to be adopted for a variety of applications. Some of these applications require real-time 2D graphics processing running on limited design specifications such as low power consumption and a small area. In order to satisfy such conditions, including a specific 2D graphics accelerator in the embedded system is an effective method. This method reduces the workload of the processor in the embedded system by exploiting the accelerator. The accelerator assists the system to perform 2D graphics processing in real-time. Therefore, a variety of applications that require 2D graphics processing can be implemented with an embedded processor. In this paper, we present a 2D graphics accelerator for tiny embedded systems. The accelerator includes an optimized line-drawing operation based on Bresenham’s algorithm. The optimized operation enables the accelerator to deal with various kinds of 2D graphics processing and to perform the line-drawing instead of the system processor. Moreover, the accelerator also distributes the workload of the processor core by removing the need for the core to access the frame buffer memory. We measure the performance of the accelerator by implementing the processor, including the accelerator, on a field-programmable gate array (FPGA), and ascertaining the possibility of realization by synthesizing using the 180 nm CMOS process.

Reform of embedded system experiment course based on engineering education accreditation

2020 ◽  
pp. 002072092091815
Author(s):  
Yong Luo ◽  
Shuai-Bing Qin ◽  
Dong-Shu Wang
Keyword(s):  
Education Reform ◽  
Embedded System ◽  
Engineering Education ◽  
Assessment Method ◽  
Teaching Model ◽  
Electronic Information ◽  
Course Content ◽  
Practical Operation ◽  
System Experiment ◽  
The Embedded System

With the continuous development of engineering education accreditation in China, its concept has had a profound impact on the reform of various majors in higher education. Using the idea of engineering education accreditation, this paper discusses the main problems in the implementation of embedded experimental courses of electronic information majors and proposes related education reform programs. Taking the embedded system experiment course of the automation major and embedded system major of Zhengzhou University as examples, the course has carried out research on the aspects of teaching model, experimental course content, scientific assessment method, etc., and proposed corresponding improvement methods to achieve better effect. The practical operation result has proved that the embedded system experiment course of the automation major and embedded system major improved the students’ ability and met the requirements of professional accreditation.

Structure of an Embedded System Software Platform for Plate Recognition System Based on Applied Mechanics

2012 ◽  
Vol 460 ◽  
pp. 266-270
Author(s):  
Xing Wu Sun ◽  
Yu Chen ◽  
Ai Fei Wang
Keyword(s):  
Embedded System ◽  
Recognition System ◽  
Cmos Camera ◽  
Camera System ◽  
New Thought ◽  
Development Platform ◽  
Embedded Linux System ◽  
Acquisition Device ◽  
The Embedded System ◽  
And Control

According to the shortcomings of large volume and high cost about the plate recognition system, an embedded plate recognition system is developed based on the ARM11 processor at lower costs. Taking the embedded Linux system as the software development platform, the system uses graphical user interface to operate and control the machine. Using CMOS camera system as image acquisition device, the system adopts HSV algorithm to realize the image classification on the platform of the embedded plate recognition system. The experimental results show that the embedded system runs stably, can realize the plate classification by color, and has the advantages of small size, low power consumption, convenience for using and so on. The embedded system provides a new thought for plate recognition.

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