An Improved BIST Algorithm Research

2014 ◽  
Vol 926-930 ◽  
pp. 2959-2963
Author(s):  
Ming Xiao Ma

This paper presents an improved algorithm of test vector based on GA and LFSR method, to improve the TPG first, then using GA and LFSR algorithm generate test vector, finally establish the algorithm to test vector for sorting, make the bit jump number of sorted sequence at least, and uses the improved output circuit TC test method are analyzed in the response, through the experimental data, verify the advantages of this scheme is to improve the test fault coverage, reduce power consumption and improve test speed.

2018 ◽  
Vol 27 (05) ◽  
pp. 1850078 ◽  
Author(s):  
J. Praveen ◽  
M. N. Shanmukha Swamy

In several pseudorandom built-in self-test (BIST) circuits, the applied test vectors will be generated by a linear feedback shift register (LFSR). This type of test pattern generator (TPG) may generate some repeated test patterns, which unnecessarily increases the test power without contributing much to the fault coverage. Based on the vast designs of TPG engine, the chip area also increases by contributing for the overall power consumption of the IC. This paper presents an approach called low power — bit complements test vector generation (LP-BCTVG) technique with bipartite (half fixed) and bit insertion (either 0 or 1) techniques. In order to reduce the test power, the LP-BCTVG inserts appropriate intermediate vectors in between consecutive test vectors generated by LFSR circuit. Hence, the application of final output vectors of LP-BCTVG circuit over circuit under test decreases the test power compared with LFSR-based BIST. By complementing the output bits of LP-BCTVG, we can reduce the bulkiness of TPG engine approximately by half. This further contributes to the reduced IC size. The obtained simulation results prove that this technique can reduce the overall test power consumption along with better fault coverage when compared with LFSR-based BIST and other recent methods. Here, the proposed approach has been tested on several ISCAS’85, ISCAS’89 and ITC’99 benchmark circuits.


2014 ◽  
Vol E97.B (12) ◽  
pp. 2698-2705
Author(s):  
Tomoyuki HINO ◽  
Hitoshi TAKESHITA ◽  
Kiyo ISHII ◽  
Junya KURUMIDA ◽  
Shu NAMIKI ◽  
...  

2009 ◽  
Vol 63 (2) ◽  
Author(s):  
Joanna Karcz ◽  
Beata Mackiewicz

AbstractThe effects of baffling of an agitated vessel on the production of floating particles suspension are presented in this paper. Critical agitator speed, needed for particles dispersion in a liquid agitated in a vessel of the inner diameter of 0.295 m, was determined. The just drawdown agitator speeds were defined analogously to the Zwietering criterion. Specific agitation energy was calculated from the power consumption experimental data obtained by means of the strain gauge method. The experiments were carried out for twelve configurations of the baffles differing in number, length and their arrangement in the vessels. The following high-speed impellers were used: up- and downpumping six blade pitched blade turbines, Rushton turbine, and propeller. The impeller was located in the vessel in the height equal to two-thirds or one-third of the vessel diameter from the bottom of the vessel. The results were described in the form of a dimensionless equation.


Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2505
Author(s):  
Mariusz Węgrzyn ◽  
Ernest Jamro ◽  
Agnieszka Dąbrowska-Boruch ◽  
Kazimierz Wiatr

Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT memory is vulnerable to single-event upset (SEU) mainly caused by cosmic radiations. Consequently, in this paper, we used combined SEU-induced and stuck-at fault models to simulate every possible fault. The test program written in an assembler was based on the bijective property. Furthermore, the fault detection matrix was determined, and this matrix describes the detectability of every fault by every test vector. The major novelty of this paper is the optimal reduction in the number of required test vectors in such a way that fault coverage is not reduced. Furthermore, this paper also studied the optimal selection of test vectors when only 95% maximal fault coverage is acceptable; in such a case, only three test vectors are required. Further, local and global test vector selection is also described.


2014 ◽  
Vol 136 (6) ◽  
Author(s):  
Mathias Beer ◽  
Yves-Simon Gloy ◽  
Mohit Raina ◽  
Thomas Gries

The crochet knitting machine is a warp knitting machine with a weft insertion system placed on a weft guide bar. On standard machines, the weft guide bar is made from aluminum and weighs about 570 g. The single-drive motors, which power the bar, account for 15–20% of the machines total power consumption. The aim of this research was to reduce power consumption by decreasing the mass of the weft guide bar. This was done by constructing the bar from carbon fiber reinforced plastics rather than aluminum, resulting in a mass saving of 260 g.


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