scholarly journals Optimal Reduction in the Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2505
Author(s):  
Mariusz Węgrzyn ◽  
Ernest Jamro ◽  
Agnieszka Dąbrowska-Boruch ◽  
Kazimierz Wiatr
Keyword(s):  
Fault Coverage ◽  
Test Vector ◽  
Single Event Upset ◽  
Fault Models ◽  
Test Program ◽  
Global Test ◽  
Test Vectors ◽  
Processor Cores ◽  
Optimal Reduction ◽  
Selection Of

Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT memory is vulnerable to single-event upset (SEU) mainly caused by cosmic radiations. Consequently, in this paper, we used combined SEU-induced and stuck-at fault models to simulate every possible fault. The test program written in an assembler was based on the bijective property. Furthermore, the fault detection matrix was determined, and this matrix describes the detectability of every fault by every test vector. The major novelty of this paper is the optimal reduction in the number of required test vectors in such a way that fault coverage is not reduced. Furthermore, this paper also studied the optimal selection of test vectors when only 95% maximal fault coverage is acceptable; in such a case, only three test vectors are required. Further, local and global test vector selection is also described.

scholarly journals Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA

2021 ◽  
Author(s):  
Mariusz Węgrzyn ◽  
Ernest Jamro ◽  
Agnieszka Dąbrowska-Boruch ◽  
Kazimierz Wiatr
Keyword(s):  
Test Data ◽  
Dynamic Reconfiguration ◽  
Experimental Results ◽  
Testing Time ◽  
Industrial Testing ◽  
Difficult Condition ◽  
Optimization Methodology ◽  
Test Vectors ◽  
Processor Cores ◽  
Optimal Reduction

This paper describes a new optimization methodology of testing vector sets reduction for testing of soft-processor cores and their individual blocks. The deterministic test vectors both for whole core and its individual blocks are investigated that significantly reduce the testing time and amount of test data that needs to be stored on the tester memory. The processor executes an assembler program which together with determined testing vectors ex-ercise its functionality. The new BIST methodology applicable at industrial testing of processor cores, diagnostics and dynamic reconfiguration of FPGA is proposed. This novel methodology combined with dynamic reconfiguration of FPGAs can be profitable applied for missions-critical i.e. FPGAs operate in space, or other difficult condition where are explore on radiation. Experimental results demonstrate that the proposed approach reduces many times testing time.

scholarly journals Antirandom Testing: A Distance-Based Approach

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Shen Hui Wu ◽  
Sridhar Jandhyala ◽  
Yashwant K. Malaiya ◽  
Anura P. Jayasumana
Keyword(s):  
Vector Space ◽  
Fault Coverage ◽  
Random Testing ◽  
Test Vector ◽  
Bridging Faults ◽  
New Approach ◽  
Maximum Extent ◽  
Total Distance ◽  
Test Vectors

Random testing requires each test to be selected randomly regardless of the tests previously applied. This paper introduces the concept of antirandom testing where each test applied is chosen such that its total distance from all previous tests is maximum. This spans the test vector space to the maximum extent possible for a given number of vectors. An algorithm for generating antirandom tests is presented. Compared with traditional pseudorandom testing, antirandom testing is found to be very effective when a high-fault coverage needs to be achieved with a limited number of test vectors. The superiority of the new approach is even more significant for testing bridging faults.

BIST-Based Low Power Test Vector Generator and Minimizing Bulkiness of VLSI Architecture

2018 ◽  
Vol 27 (05) ◽  
pp. 1850078 ◽  
Author(s):  
J. Praveen ◽  
M. N. Shanmukha Swamy
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Vlsi Architecture ◽  
Fault Coverage ◽  
Linear Feedback ◽  
Test Vector ◽  
Test Power ◽  
Chip Area ◽  
Test Vector Generator ◽  
Test Vectors

In several pseudorandom built-in self-test (BIST) circuits, the applied test vectors will be generated by a linear feedback shift register (LFSR). This type of test pattern generator (TPG) may generate some repeated test patterns, which unnecessarily increases the test power without contributing much to the fault coverage. Based on the vast designs of TPG engine, the chip area also increases by contributing for the overall power consumption of the IC. This paper presents an approach called low power — bit complements test vector generation (LP-BCTVG) technique with bipartite (half fixed) and bit insertion (either 0 or 1) techniques. In order to reduce the test power, the LP-BCTVG inserts appropriate intermediate vectors in between consecutive test vectors generated by LFSR circuit. Hence, the application of final output vectors of LP-BCTVG circuit over circuit under test decreases the test power compared with LFSR-based BIST. By complementing the output bits of LP-BCTVG, we can reduce the bulkiness of TPG engine approximately by half. This further contributes to the reduced IC size. The obtained simulation results prove that this technique can reduce the overall test power consumption along with better fault coverage when compared with LFSR-based BIST and other recent methods. Here, the proposed approach has been tested on several ISCAS’85, ISCAS’89 and ITC’99 benchmark circuits.

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors

2008 ◽  
Vol E91-A (12) ◽  
pp. 3506-3513 ◽  
Author(s):  
Y. HIGAMI ◽  
K. K. SALUJA ◽  
H. TAKAHASHI ◽  
S.-y. KOBAYASHI ◽  
Y. TAKAMATSU
Keyword(s):  
Fault Coverage ◽  
Test Vectors

Real-Time Tsunami Prediction System Using DONET

2017 ◽  
Vol 12 (4) ◽  
pp. 766-774 ◽  
Author(s):  
Narumi Takahashi ◽  
Kentaro Imai ◽  
Masanobu Ishibashi ◽  
Kentaro Sueki ◽  
Ryoko Obayashi ◽  
...  
Keyword(s):  
Real Time ◽  
Time Lag ◽  
Rupture Zone ◽  
Tsunami Source ◽  
Earthquake Rupture ◽  
Prediction System ◽  
Fault Models ◽  
Tsunami Height ◽  
Inundation Area ◽  
Selection Of

We constructed a real-time tsunami prediction system using the Dense Oceanfloor Network System for Earthquakes and Tsunamis (DONET). This system predicts the arrival time of a tsunami, the maximum tsunami height, and the inundation area around coastal target points by extracting the proper fault models from 1,506 models based on the principle of tsunami amplification. Since DONET2, installed in the Nankai earthquake rupture zone, was constructed in 2016, it has been used in addition to DONET1 installed in the Tonankai earthquake rupture zone; we revised the system using both DONET1 and DONET2 to improve the accuracy of tsunami prediction. We introduced a few methods to improve the prediction accuracy. One is the selection of proper fault models from the entire set of models considering the estimated direction of the hypocenter using seismic and tsunami data. Another is the dynamic selection of the proper DONET observatories: only DONET observatories located between the prediction point and tsunami source are used for prediction. Last is preparation for the linked occurrence of double tsunamis with a time-lag. We describe the real-time tsunami prediction system using DONET and its implementation for the Shikoku area.

scholarly journals Influence of Orbital Parameters on SEU Rate of Low-Energy Proton in Nano-SRAM Device

Symmetry ◽  
2020 ◽  
Vol 12 (12) ◽  
pp. 2030
Author(s):  
Bing Ye ◽  
Li-Hua Mo ◽  
Tao Liu ◽  
You-Mei Sun ◽  
Jie Liu
Keyword(s):  
Heavy Ion ◽  
High Energy ◽  
Low Energy ◽  
Single Event Upset ◽  
Single Event ◽  
High Energy Proton ◽  
Orbital Parameters ◽  
Energy Proton ◽  
Orbital Height ◽  
Selection Of

The on-orbit single-event upset (SEU) rate of nanodevices is closely related to the orbital parameters. In this paper, the on-orbit SEU rate (OOSR) induced by a heavy ion (HI), high-energy proton (HEP) and low-energy proton (LEP) for a 65 nm SRAM device is calculated by using the software SPACE RADIATION under different orbits based on the experimental data. The results indicate that the OOSR induced by the HI, HEP and LEP varies with the orbital parameters. In particular, the orbital height, inclination and shieling thickness are the key parameters that affect the contribution of the LEP to the total OOSR. Our results provide guidance for the selection of nanodevices on different orbits.

A Coating Evaluation Testing Program★

CORROSION ◽  
1958 ◽  
Vol 14 (12) ◽  
pp. 18-24 ◽  
Author(s):  
E. R. ALLEN
Keyword(s):  
Field Performance ◽  
Service Performance ◽  
New Materials ◽  
Test Program ◽  
Test Procedures ◽  
Controlled System ◽  
Field Service ◽  
Laboratory Results ◽  
Laboratory Procedures ◽  
Selection Of

Abstract A program to test and evaluate external pipeline coatings is described. When this program was started ten years ago, many methods and procedures then in use did not give all of the information desired. Field burial tests are lengthly and because of the variable conditions which govern results can neither be controlled nor evaluated with any precision. Only laboratory type tests are suitable for a closely controlled system of coating evaluation. Laboratory results must be correlated with field service performance. This test program was in three phases: First, laboratory procedures and apparatus were developed. Second, commonly used coatings were tested ana laboratory results correlated with field performance data. Third, new materials were tested and their performance compared with coatings in common use. Laboratory and field test procedures and apparatus are described. A discussion on the application of test data to selection of pipeline coatings is included. 2.1.2

THAI Multi-Compartment Containment Test Program

2006 ◽  
Author(s):  
T. Kanzleiter ◽  
G. Poss ◽  
F. Funke ◽  
H.-J. Allelein
Keyword(s):  
Fission Product ◽  
Combined Effect ◽  
Severe Accident ◽  
Test Facility ◽  
Test Program ◽  
Broad Variety ◽  
Containment Test ◽  
Accident Conditions ◽  
Selection Of ◽  
Future Test

The THAI experimental programme includes combined-effect investigations on thermal hydraulics, hydrogen, and fission product (iodine and aerosols) behaviour in LWR containments under severe accident conditions. An overview on the experiments performed up to now and on the future test program is presented, in combination with a selection of typical results to illustrate the versatility of the test facility and the broad variety of topics investigated.

scholarly journals Adjustable PRPG for Low Power Test Patterns

2021 ◽  
Vol 9 (6) ◽  
pp. 195-201
Author(s):  
Nadimulla B. ◽  
Aruna Mastani, S.
Keyword(s):  
Power Consumption ◽  
Binary Sequences ◽  
Testing Time ◽  
Test Vector ◽  
Power Test ◽  
Low Power Test ◽  
Simulation Results ◽  
Self Test ◽  
Set Compression ◽  
Test Vectors

As the power consumption is more in the processes of testing, test vector set compression and controlling of toggling plays a crucial role in reducing the power consumption during test mode. In exploring the controlling techniques of toggling, Pre-Selected Toggling (PRESTO) of test patterns is a technique that can control the toggling of a test patterns in a precise manner in Built-in Self -Test (BIST) architectures. In this paper we modify the architecture of existing Full Version PRESTO that can be used to generate test vectors and in addition binary sequences used as scan chins such that the controlling of sequence of test vectors depends on number of 1’s present in the switch code which is user defined thus reducing the testing time with significant fault coverage, and in addition the optimization is also observed in area and power. The area has decreased by 12.2% and power consumption by 15.43%. The Synthesis and implementation of the architectures are done using Artix7 (xc7a100tcsg324-3) FPGA family. The simulation results have been analyzed through Mentor-graphics Questa-sim 10.7C

Loop Transformation Algorithm for Test Vector Accessing at High Speed

2019 ◽  
Author(s):  
Bjorn Dahlberg ◽  
Martin Versen
Keyword(s):  
Failure Analysis ◽  
High Speed ◽  
Semiconductor Devices ◽  
Test Vector ◽  
Memory Architecture ◽  
Critical Importance ◽  
Loop Transformation ◽  
Test Speed ◽  
Transformation Algorithm ◽  
Test Vectors

Abstract Looping on test vectors is a widespread requirement in failure analysis of semiconductor devices. The start of the loop and the number of vectors in the loop can be of critical importance. Present-day vector memory architecture tends to impose restrictions on both due to test speed requirements. A new Vector Loop Transformation algorithm is introduced to remedy the tester constraints.

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