An All Silicon Carbide High Temperature (450+ °C) High Voltage Gain AC Coupled Differential Amplifier

2011 ◽  
Vol 679-680 ◽  
pp. 746-749
Author(s):  
Jie Yang ◽  
John Fraley ◽  
Bryon Western ◽  
Marcelo Schupbach ◽  
Alexander B. Lostetter

APEI, Inc. designed, fabricated and tested a high gain AC coupled differential amplifier based on a custom-built silicon carbide (SiC) vertical junction field effect transistor (VJFET). This SiC differential amplifier is capable of extreme temperature operation up to 450 °C, at which a high differential voltage gain of more than 47 dB is maintained. This high gain AC coupled differential amplifier can be integrated with high temperature sensors that deliver weak AC output signals to improve signal quality and noise immunity.

2012 ◽  
Vol 717-720 ◽  
pp. 1253-1256
Author(s):  
Jie Yang ◽  
John Fraley ◽  
Bryon Western ◽  
Marcelo Schupbach ◽  
Alexander B. Lostetter

APEI, Inc. designed, fabricated and tested a high gain AC coupled differential amplifier based on a custom-built silicon carbide (SiC) vertical junction field effect transistor (VJFET). This SiC differential amplifier is capable of high temperature operation up to 450 °C, at which a high differential voltage gain of more than 47 dB is maintained. This high gain AC coupled differential amplifier can be integrated with harsh environment sensors that deliver weak AC output signals to improve signal quality and noise immunity.


2020 ◽  
Vol 1004 ◽  
pp. 1148-1155 ◽  
Author(s):  
David J. Spry ◽  
Philip G. Neudeck ◽  
Carl W. Chang

While NASA Glenn Research Center’s “Generation 10” 4H-SiC Junction Field Effect Transistor (JFET) integrated circuits (ICs) have uniquely demonstrated 500 °C electrical operation for durations of over a year, this experimental work has also revealed that physical cracking of chip dielectric passivation layers ultimately limits extreme-environment operating lifetime [1-3]. The prevention of such dielectric passivation cracks should therefore improve IC high temperature durability and yield, leading to more beneficial technology adoption into aerospace, automotive, and energy systems. This report describes Generation 10.2, 11.1, and 11.2 die tested under unbiased and unpackaged accelerated age testing at 500 °C, 600 °C, 720 °C, and 800 °C in air-atmosphere ovens for 100-and 200-hour duration. Additional samples were separately subjected to 10 thermal cycles between the same high temperatures (with 10-hour high-temperature soak each cycle) and 50 °C. It is shown that having two stoichiometric Si3N4 layers in the interconnect dielectric stack substantially decreases the amount of dielectric cracking observed following these oven tests.


Author(s):  
Frederick Ojiemhende Ehiagwina ◽  
Olufemi Oluseye Kehinde ◽  
Lateef Olashile Afolabi ◽  
Hassan Jimoh Onawola ◽  
Nurudeen Ajibola Iromini

Properties of Silicon Carbide Junction Field Effect Transistor (SiC JFET) such as high switching speed, low forward voltage drop and high temperature operation have attracted the interest of power electronic researchers and technologists, who for many years developed devices based on Silicon (Si).  A number of power system Engineers have made efforts to develop more robust equipment including circuits or modules with higher power density. However, it was realized that several available power semiconductor devices were approaching theoretical limits offered by Si material with respect to capability to block high voltage, provide low on-state voltage drop and switch at high frequencies. This paper presents an overview of the current applications of SiC JFET in circuits such as inverters, rectifiers and amplifiers. Other areas of application reviewed include; usage of the SiC JFET in pulse signal circuits and boost converters. Efforts directed toward mitigating the observed increase in electromagnetic interference were also discussed. It also presented some areas for further research, such as having more applications of SiC JFET in harsh, high temperature environment. More work is needed with regards to SiC JFET drivers so as to ensure stable and reliable operation, and reduction in the prices of SiC JFETs through mass production by industries.


2016 ◽  
Vol 13 (2) ◽  
pp. 39-50 ◽  
Author(s):  
Zheng Chen ◽  
Yiying Yao ◽  
Wenli Zhang ◽  
Dushan Boroyevich ◽  
Khai Ngo ◽  
...  

This article presents a 1,200-V, 120-A silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) phase-leg module capable of operating at 200°C ambient temperature. Paralleling six 20-A MOSFET bare dice for each switch, this module outperforms the commercial SiC modules in higher operating temperature and lower package parasitics at a comparable power rating. The module's high-temperature capability is validated through the extensive characterizations of the SiC MOSFET, as well as the careful selections of suitable packaging materials. Particularly, the sealed-step-edge technology is implemented on the direct-bonded-copper substrates to improve the module's thermal cycling lifetime. Though still based on the regular wire-bond structure, the module is able to achieve over 40% reduction in the switching loop inductance compared with a commercial SiC module by optimizing its internal layout. By further embedding decoupling capacitors directly on the substrates, the module also allows SiC MOSFETs to be switched twice faster with only one-third turn-off overvoltages compared with the commercial module.


2020 ◽  
Vol 209 (1) ◽  
pp. 11-18
Author(s):  
Xianjun Zhang ◽  
Na Li ◽  
Mingjia Wang ◽  
Qingliang Qin ◽  
Haohua Qin ◽  
...  

2017 ◽  
Vol 897 ◽  
pp. 567-570 ◽  
Author(s):  
Philip G. Neudeck ◽  
David J. Spry ◽  
Liang Yu Chen ◽  
Dorothy Lukco ◽  
Carl W. Chang ◽  
...  

Prolonged 500 °C to 700 °C electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T ≥ 500 °C durability-limiting IC failure initiates with thermal stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.


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