Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 °C to 700 °C

2017 ◽  
Vol 897 ◽  
pp. 567-570 ◽  
Author(s):  
Philip G. Neudeck ◽  
David J. Spry ◽  
Liang Yu Chen ◽  
Dorothy Lukco ◽  
Carl W. Chang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Field Effect Transistor ◽  
Crack Formation ◽  
Extreme Temperature ◽  
Testing Data ◽  
Passivation Layers ◽  
Microscopic Studies ◽  
Study Support ◽  
Effect Transistor ◽  
Microelectronics Technology

Prolonged 500 °C to 700 °C electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T ≥ 500 °C durability-limiting IC failure initiates with thermal stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.

Experimental Study on Mitigation of Lifetime-Limiting Dielectric Cracking in Extreme Temperature 4H-SiC JFET Integrated Circuits

2020 ◽  
Vol 1004 ◽  
pp. 1148-1155 ◽  
Author(s):  
David J. Spry ◽  
Philip G. Neudeck ◽  
Carl W. Chang
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Field Effect Transistor ◽  
Extreme Temperature ◽  
Energy Systems ◽  
Extreme Environment ◽  
Air Atmosphere ◽  
Passivation Layers ◽  
Operating Lifetime ◽  
Effect Transistor

While NASA Glenn Research Center’s “Generation 10” 4H-SiC Junction Field Effect Transistor (JFET) integrated circuits (ICs) have uniquely demonstrated 500 °C electrical operation for durations of over a year, this experimental work has also revealed that physical cracking of chip dielectric passivation layers ultimately limits extreme-environment operating lifetime [1-3]. The prevention of such dielectric passivation cracks should therefore improve IC high temperature durability and yield, leading to more beneficial technology adoption into aerospace, automotive, and energy systems. This report describes Generation 10.2, 11.1, and 11.2 die tested under unbiased and unpackaged accelerated age testing at 500 °C, 600 °C, 720 °C, and 800 °C in air-atmosphere ovens for 100-and 200-hour duration. Additional samples were separately subjected to 10 thermal cycles between the same high temperatures (with 10-hour high-temperature soak each cycle) and 50 °C. It is shown that having two stoichiometric Si3N4 layers in the interconnect dielectric stack substantially decreases the amount of dielectric cracking observed following these oven tests.

scholarly journals A Study on the Effect of the Structural Parameters and Internal Mechanism of a Bilateral Gate-Controlled S/D Symmetric and Interchangeable Bidirectional Tunnel Field Effect Transistor

2021 ◽  
Vol 16 (1) ◽  
Author(s):  
Xiaoshi Jin ◽  
Yicheng Wang ◽  
Kailu Ma ◽  
Meile Wu ◽  
Xi Liu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Structural Parameters ◽  
Cmos Integrated Circuits ◽  
Region Length ◽  
Internal Mechanism ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Switching Characteristics

AbstractA bilateral gate-controlled S/D symmetric and interchangeable bidirectional tunnel field effect transistor (B-TFET) is proposed in this paper, which shows the advantage of bidirectional switching characteristics and compatibility with CMOS integrated circuits compared to the conventional asymmetrical TFET. The effects of the structural parameters, e.g., the doping concentrations of the N+ region and P+ region, length of the N+ region and length of the intrinsic region, on the device performances, e.g., the transfer characteristics, Ion–Ioff ratio and subthreshold swing, and the internal mechanism are discussed and explained in detail.

Prolonged 500°C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

2018 ◽  
Vol 924 ◽  
pp. 949-952 ◽  
Author(s):  
David J. Spry ◽  
Philip G. Neudeck ◽  
Dorothy Lukco ◽  
Liang Yu Chen ◽  
Michael J. Krasowski ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Earth Atmosphere ◽  
Surface Atmosphere ◽  
Effect Transistor ◽  
Output Characteristics ◽  
Technology Demonstrator

This report describes more than 5000 hours of successful 500 °C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 °C. After 100 hours of 500 °C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 °C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 °C in comparison to what is observed for Earth-atmosphere oven testing at 500 °C.

scholarly journals Dynamic pH Sensor with Embedded Calibration Scheme by Advanced CMOS FinFET Technology

Sensors ◽  
2019 ◽  
Vol 19 (7) ◽  
pp. 1585 ◽  
Author(s):  
Chien-Ping Wang ◽  
Ying-Chun Shen ◽  
Peng-Chun Liou ◽  
Yu-Lun Chueh ◽  
Yue-Der Chih ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Field Effect Transistor ◽  
Noise Analysis ◽  
Ph Sensor ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
New Device ◽  
Sensors Array ◽  
Effect Transistor ◽  
Readout Scheme

In this work, we present a novel pH sensor using efficient laterally coupled structure enabled by Complementary Metal-Oxide Semiconductor (CMOS) Fin Field-Effect Transistor (FinFET) processes. This new sensor features adjustable sensitivity, wide sensing range, multi-pad sensing capability and compatibility to advanced CMOS technologies. With a self-balanced readout scheme and proposed corresponding circuit, the proposed sensor is found to be easily embedded into integrated circuits (ICs) and expanded into sensors array. To ensure the robustness of this new device, the transient response and noise analysis are performed. In addition, an embedded calibration operation scheme is implemented to prevent the proposed sensing device from the background offset from process variation, providing reliable and stable sensing results.

scholarly journals Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

2016 ◽  
Vol 858 ◽  
pp. 1112-1116 ◽  
Author(s):  
David J. Spry ◽  
Philip G. Neudeck ◽  
Liang Yu Chen ◽  
Laura J. Evans ◽  
Dorothy Lukco ◽  
...  
Keyword(s):  
Conference Proceedings ◽  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Failure Mechanisms ◽  
Operating Time ◽  
Test Conditions ◽  
Effect Transistor ◽  
Physical Degradation

The fabrication and prolonged 500 °C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 °C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 °C operating time. Evidence is presented for four distinct issues that significantly impacted 500 °C IC operational yield and lifetime for this wafer.

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