Experimental Study on Mitigation of Lifetime-Limiting Dielectric Cracking in Extreme Temperature 4H-SiC JFET Integrated Circuits

2020 ◽  
Vol 1004 ◽  
pp. 1148-1155 ◽  
Author(s):  
David J. Spry ◽  
Philip G. Neudeck ◽  
Carl W. Chang
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Field Effect Transistor ◽  
Extreme Temperature ◽  
Energy Systems ◽  
Extreme Environment ◽  
Air Atmosphere ◽  
Passivation Layers ◽  
Operating Lifetime ◽  
Effect Transistor

While NASA Glenn Research Center’s “Generation 10” 4H-SiC Junction Field Effect Transistor (JFET) integrated circuits (ICs) have uniquely demonstrated 500 °C electrical operation for durations of over a year, this experimental work has also revealed that physical cracking of chip dielectric passivation layers ultimately limits extreme-environment operating lifetime [1-3]. The prevention of such dielectric passivation cracks should therefore improve IC high temperature durability and yield, leading to more beneficial technology adoption into aerospace, automotive, and energy systems. This report describes Generation 10.2, 11.1, and 11.2 die tested under unbiased and unpackaged accelerated age testing at 500 °C, 600 °C, 720 °C, and 800 °C in air-atmosphere ovens for 100-and 200-hour duration. Additional samples were separately subjected to 10 thermal cycles between the same high temperatures (with 10-hour high-temperature soak each cycle) and 50 °C. It is shown that having two stoichiometric Si3N4 layers in the interconnect dielectric stack substantially decreases the amount of dielectric cracking observed following these oven tests.

Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 °C to 700 °C

2017 ◽  
Vol 897 ◽  
pp. 567-570 ◽  
Author(s):  
Philip G. Neudeck ◽  
David J. Spry ◽  
Liang Yu Chen ◽  
Dorothy Lukco ◽  
Carl W. Chang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Field Effect Transistor ◽  
Crack Formation ◽  
Extreme Temperature ◽  
Testing Data ◽  
Passivation Layers ◽  
Microscopic Studies ◽  
Study Support ◽  
Effect Transistor ◽  
Microelectronics Technology

Prolonged 500 °C to 700 °C electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T ≥ 500 °C durability-limiting IC failure initiates with thermal stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.

An All Silicon Carbide High Temperature (450+ °C) High Voltage Gain AC Coupled Differential Amplifier

2011 ◽  
Vol 679-680 ◽  
pp. 746-749
Author(s):  
Jie Yang ◽  
John Fraley ◽  
Bryon Western ◽  
Marcelo Schupbach ◽  
Alexander B. Lostetter
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Field Effect Transistor ◽  
Extreme Temperature ◽  
High Gain ◽  
Differential Amplifier ◽  
Signal Quality ◽  
Voltage Gain ◽  
High Voltage Gain ◽  
Effect Transistor

APEI, Inc. designed, fabricated and tested a high gain AC coupled differential amplifier based on a custom-built silicon carbide (SiC) vertical junction field effect transistor (VJFET). This SiC differential amplifier is capable of extreme temperature operation up to 450 °C, at which a high differential voltage gain of more than 47 dB is maintained. This high gain AC coupled differential amplifier can be integrated with high temperature sensors that deliver weak AC output signals to improve signal quality and noise immunity.

Silicon Carbide Junction Field Effect Transistor Compact Model for Extreme Environment Integrated Circuit Design

2021 ◽  
Vol 2021 (HiTEC) ◽  
pp. 000118-000122
Author(s):  
S. Perez ◽  
A.M. Francis ◽  
J. Holmes ◽  
T. Vrotsos
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Extreme Environment ◽  
Integrated Circuit Design ◽  
Device Model ◽  
Effect Transistor ◽  
R Process

Abstract Presented is a temperature and geometry scalable 800°C Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) compact device model designed to simulate the small signal effects of the SiC JFET-R process developed by NASA Glenn Research Center. With the JFET-R process pushing the temperature limits of integrated circuits, a high-fidelity device model capable of predicting the performance over temperature and geometry is required to realize the thermal ruggedness this process provides. A high temperature (HT) packaging system was utilized to characterize a SiC JFET device up to 800°C with a dwell time of 9 hours during a single test. Invaluable device characterization data was obtained and utilized to extend the device model presented to simulate SiC JFET performance continuously over 800°C.

scholarly journals A Study on the Effect of the Structural Parameters and Internal Mechanism of a Bilateral Gate-Controlled S/D Symmetric and Interchangeable Bidirectional Tunnel Field Effect Transistor

2021 ◽  
Vol 16 (1) ◽  
Author(s):  
Xiaoshi Jin ◽  
Yicheng Wang ◽  
Kailu Ma ◽  
Meile Wu ◽  
Xi Liu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Structural Parameters ◽  
Cmos Integrated Circuits ◽  
Region Length ◽  
Internal Mechanism ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Switching Characteristics

AbstractA bilateral gate-controlled S/D symmetric and interchangeable bidirectional tunnel field effect transistor (B-TFET) is proposed in this paper, which shows the advantage of bidirectional switching characteristics and compatibility with CMOS integrated circuits compared to the conventional asymmetrical TFET. The effects of the structural parameters, e.g., the doping concentrations of the N+ region and P+ region, length of the N+ region and length of the intrinsic region, on the device performances, e.g., the transfer characteristics, Ion–Ioff ratio and subthreshold swing, and the internal mechanism are discussed and explained in detail.

Development of an SiC Multichip Phase-Leg Module for High-Temperature and High-Frequency Applications

2016 ◽  
Vol 13 (2) ◽  
pp. 39-50 ◽  
Author(s):  
Zheng Chen ◽  
Yiying Yao ◽  
Wenli Zhang ◽  
Dushan Boroyevich ◽  
Khai Ngo ◽  
...  
Keyword(s):  
High Temperature ◽  
High Frequency ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Operating Temperature ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Packaging Materials ◽  
Temperature Capability ◽  
Effect Transistor

This article presents a 1,200-V, 120-A silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) phase-leg module capable of operating at 200°C ambient temperature. Paralleling six 20-A MOSFET bare dice for each switch, this module outperforms the commercial SiC modules in higher operating temperature and lower package parasitics at a comparable power rating. The module's high-temperature capability is validated through the extensive characterizations of the SiC MOSFET, as well as the careful selections of suitable packaging materials. Particularly, the sealed-step-edge technology is implemented on the direct-bonded-copper substrates to improve the module's thermal cycling lifetime. Though still based on the regular wire-bond structure, the module is able to achieve over 40% reduction in the switching loop inductance compared with a commercial SiC module by optimizing its internal layout. By further embedding decoupling capacitors directly on the substrates, the module also allows SiC MOSFETs to be switched twice faster with only one-third turn-off overvoltages compared with the commercial module.

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