Efficient Design of QCA Adder Structures

2007 ◽  
Vol 121-123 ◽  
pp. 553-556 ◽  
Author(s):  
Sansiri Haruehanroengra ◽  
Wei Wang

Optimizing arithmetic primitives such as quantum-dot cellular automata (QCA) adders is important for investigating high-performance QCA computers in this emerging nano-technological paradigm. In this paper, we demonstrate that QCA ripple carry adder and bit-serial adder designs actually outperform carry-look-ahead and carry-select adder designs because of the increase in required interconnects. Simulation results obtained by using the QCADesigner tool for the proposed adder designs are also presented.

Optik ◽  
2016 ◽  
Vol 127 (15) ◽  
pp. 6172-6182 ◽  
Author(s):  
Trailokya Nath Sasamal ◽  
Ashutosh Kumar Singh ◽  
Anand Mohan

Author(s):  
Ms. Mayuri Ingole

Utilization of power is a major aspect in the design of integrated circuits. Since, adders are mostly employed in these circuits, we should design them effectively. Here, we propose an easy and effective method in decreasing the maximum consumption of power. Carry Select Adder is the one which is dependent on the design of two adders. We present a high performance low-power adder that is implemented. Also, here in Carry Select Adder, Binary Excess Code-1is replaced by Ripple Carry Adder. After analyzing the results, we can come to a conclusion that the architecture which is proposed will have better results in terms of consumption of power compared to conventional techniques. 


2018 ◽  
Vol 57 (11) ◽  
pp. 3419-3428 ◽  
Author(s):  
Ali Newaz Bahar ◽  
Radhouane Laajimi ◽  
Md. Abdullah-Al-Shafi ◽  
Kawsar Ahmed

2019 ◽  
Vol 21 ◽  
pp. 100252 ◽  
Author(s):  
Azath Mubarakali ◽  
Jayabrabu Ramakrishnan ◽  
Dinesh Mavaluru ◽  
Amria Elsir ◽  
Omer Elsier ◽  
...  

2019 ◽  
Vol 9 (3) ◽  
pp. 27 ◽  
Author(s):  
Majeed ◽  
Alkaldy ◽  
bin Zainal ◽  
Bin MD Nor

The quantum-dot cellular automata (QCA) nano-technique has attracted computer scientists due to its noticeable features such as low power consumption and small size. Many papers have been published in the literature about the utilization of this technology for de-signing many QCA circuits and for presenting logic gates in an optimal structure. The T flip-flop, which is an essential part of digital designs, can be used to design synchronous and asynchronous counters. This paper presents a novel T flip-flop structure in an optimal form. The presented novel gate was used to design an N-bit binary synchronous counter. The QCADesigner software was used to verify the designed circuits and to present the simulation results, while the QCAPro tool was used for the power analysis. The proposed design required minimal power and showed good improvements over previous designs.


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