scholarly journals Modified Low Power Binary to Excess Code Converter

2015 ◽  
Vol 4 (03) ◽  
pp. 06-10
Author(s):  
Ms. Mayuri Ingole
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Major Aspect ◽  
Code Converter ◽  
Ripple Carry Adder ◽  
Carry Select Adder ◽  
The One

Utilization of power is a major aspect in the design of integrated circuits. Since, adders are mostly employed in these circuits, we should design them effectively. Here, we propose an easy and effective method in decreasing the maximum consumption of power. Carry Select Adder is the one which is dependent on the design of two adders. We present a high performance low-power adder that is implemented. Also, here in Carry Select Adder, Binary Excess Code-1is replaced by Ripple Carry Adder. After analyzing the results, we can come to a conclusion that the architecture which is proposed will have better results in terms of consumption of power compared to conventional techniques. 

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

scholarly journals 4-bit Carry Look Ahead Adder Using MGDI Technique

2021 ◽  
Vol 9 (9) ◽  
pp. 855-860
Author(s):  
Shaik Mahammad Ameer Afridi
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Power Dissipation ◽  
High Performance ◽  
Digital Signal ◽  
Vlsi Circuits ◽  
Digital Vlsi ◽  
Look Ahead ◽  
Energy Trade ◽  
Integral Role

Abstract: Today's high-performance processor is built with arithmetic logic units that add and subtract key components. Design considerations related to low power and high performance digital VLSI circuits have become more prevalent in today's world. In order to develop low-power and high-performance processors, the designers need to design their adder circuits with the required speed and power dissipation for their applications. This topic introduces the concept of a adder using MGDI Technique. The Exact Speculative Carry Look Ahead Adder the use of the Modified-GDI (Modified-Gate Diffusion Input) is cautioned in this work. The delay, location and energy trade off performs a integral role in VLSI. We already comprehend that designs which are of CMOS fashion occupy extra area might also eat extra strength consumption. The switching conduct of the circuit reason the heating up of integrated circuits affects the working stipulations of the purposeful unit. The adders are the most important parts of countless applications such as microprocessors, microcontrollers and digital signal processors and additionally in actual time applications. Hence it is necessary to minimize the adder blocks to format a perfect processor. This work is proposed on a 16 bit carry seem to be in advance adder is designed through using MGDI gate and 4T XOR gates and a speculator blocks. The proposed MGDI raise Look Ahead adder occupies 68% much less region and the strength consumption and the propagation extend additionally considerably reduces when in contrast to the traditional carry Look Ahead adder why because the variety transistors extensively reduces from 1448 (Conventional) to 456 (Proposed CLA). The simulation consequences of the proposed format carried out in Xilinx. Keywords: Delay, power dissipation, voltage, transistor sizing.

A Low Power, Precision SAR Analog to Digital Converter for High Temperature Applications

2014 ◽  
Vol 2014 (HITEC) ◽  
pp. 000053-000057
Author(s):  
Jeff Watson ◽  
Maithil Pachchigar
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
High Reliability ◽  
Data Converters ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Data Converter ◽  
Precision Data ◽  
Analog To Digital

A growing number of industries are calling for low power electronics that operate reliably at temperatures of 175°C and higher. Many of these applications require a precision data acquisition signal chain in order to digitize analog data so that it can be collected and processed. Designing circuits that meet these needs can be very challenging, requiring a data converter that can deliver high performance and reliability in these harsh environments. There are currently a very limited number of integrated circuits commercially available that are specified for operation at these temperatures, and no low power precision data converters with sample rates greater than 100kSPS. This paper presents a new 210°C rated precision analog to digital converter capable of sample rates up to 600 kSPS with 16 bit resolution while maintaining low power consumption and packaged in a small form factor. We will explore the converter architecture of this ADC, present initial test results, and show how high reliability is achieved through qualification and advanced packaging techniques.

Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits

2016 ◽  
Vol 25 (11) ◽  
pp. 1650142 ◽  
Author(s):  
Kamineni Sumanth Kumar ◽  
John Reuben
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Three Dimensional ◽  
Buffer Insertion ◽  
Clock Skew ◽  
Clock Tree ◽  
Clock Tree Synthesis ◽  
3D Integrated Circuits ◽  
Tree Synthesis

Three-Dimensional (3D) Integrated Circuits (ICs) offers integrating capabilities of ‘More than Moore’ while overcoming CMOS scaling limitations, providing the advantages of low power, high performance and reduced costs. The design of the Clock Distribution Network (CDN) for a 3D IC has to be done meticulously to guarantee reliable operation. In the design of the CDN, clock buffers are crucial units that affect the clock skew, slew and power dissipated by the clock tree. In this paper, we propose a two-stage buffering technique that inserts clock buffers for slew control and skew minimization. Such a buffering technique decreases the number of buffers and power dissipated in the clock tree when compared to previous works which were inserting buffers primarily for slew control. We incorporate the proposed buffering technique into the 3D clock tree synthesis algorithm of previous work and evaluate the performance of the clock tree for both single Through-Silicon Vias (TSV) and mutiple TSV approach. When evaluated on IBM benchmarks (r1-r5), our buffering technique results in 25–28% reduction in buffer count and 25–29% reduction in power for single TSV-based 3D CDN. For multi-TSV approach, the performance of our work is even better:around 31–38% reduction in buffer count and 32–39% reduction in power.

scholarly journals Low Power and High Performance MTCMOS Conditional Discharge Flip Flop

2019 ◽  
Vol 8 (6S2) ◽  
pp. 341-345
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Leakage Power ◽  
Battery Life ◽  
Flip Flop ◽  
Circuit Performance ◽  
Processing Information ◽  
Conditional Discharge ◽  
Standby Mode

Utilization in high-performance integrated circuits has been one of the most severe limitations in models in recent years.. Conditional discharge flip flop (CDFF) related to one of the earliest pulses caused flipflop reduces internal switching activities as that of existing explicit pulse triggered Data close to output flipflop (Ep-DCO). Registers are the main parts for processing information eg: in counters, accumulators etc.,. Implementation of these registers using CDFF can achieve low power consumption and high performance. MTCMOS (multi threshold CMOS) technique saves the leakage power during standby mode operations and hence, enhances the circuit performance for long battery life applications. We find that, using both MTCMOS and conditional discharge technique in flip flop, improves the performance and also consumes low power. In this paper, we simulate CDFF and the proposed MTCMOS CDFF to prove that MTCMOS CDFF is the best among the fastest pulse triggered flipflops. We also implement an application 4 bit shift register using proposed MTCMOS conditional discharge flip flop

Design and Analysis of Low Power Hybrid Braun Multiplier using Ladner Fischer Adder

2017 ◽  
Vol 6 (03) ◽  
pp. 07-12
Author(s):  
Prof. Shweta Jain
Keyword(s):  
Low Power ◽  
High Speed ◽  
Digital Communication ◽  
Digital Filtering ◽  
Parallel Multiplier ◽  
Ripple Carry Adder ◽  
Array Multiplier ◽  
The One ◽  
Dsp Systems ◽  
Specific Array

Multiplier is important in many DSP systems and in many hardware blocks. Multiplier are used in various DSP application like digital filtering, digital communication. This needs parallel array multiplier to attain high speed for execution and better performance. A specific array multiplier is implemented known as Braun design. Braun multiplier is the one which is a kind of parallel multiplier. It contains different CSA count of AND gates. Braun multiplier employing Ripple Carry Adder is developed here having high speed PPA. It will reduce the delay and implemented using Tanner EDA tool.

An Ultra-Low-Voltage Low-Power Current-Mode True RMS-to-DC Converter

2016 ◽  
Vol 25 (06) ◽  
pp. 1650066 ◽  
Author(s):  
Pantre Kompitaya ◽  
Khanittha Kaewdang
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Complexity ◽  
Current Mode ◽  
Cmos Technology ◽  
Low Supply Voltage

A current-mode CMOS true RMS-to-DC (RMS: root-mean-square) converter with very low voltage and low power is proposed in this paper. The design techniques are based on the implicit computation and translinear principle by using CMOS transistors that operate in the weak inversion region. The circuit can operate for two-quadrant input current with wide input dynamic range (0.4–500[Formula: see text]nA) with an error of less than 1%. Furthermore, its features are very low supply voltage (0.8[Formula: see text]V), very low power consumption ([Formula: see text]0.2[Formula: see text]nW) and low circuit complexity that is suitable for integrated circuits (ICs). The proposed circuit is designed using standard 0.18[Formula: see text][Formula: see text]m CMOS technology and the HSPICE simulation results show the high performance of the circuit and confirm the validity of the proposed design technique.

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