High Resolution High Power Low Frequency Digital-to-Analog Converter

2010 ◽  
Vol 164 ◽  
pp. 133-138
Author(s):  
Vytenis Puidokas ◽  
Albinas J. Marcinkevičius
Keyword(s):  
Low Frequency ◽  
Quantization Noise ◽  
Transmission Characteristics ◽  
Sigma Delta Modulator ◽  
Digital To Analog Converter ◽  
Sigma Delta ◽  
Chip Area ◽  
Amplitude Frequency Response ◽  
Analog Converter ◽  
Output Filter

The architectural scheme of the designed Sigma-Delta DAC on the FPGA is considered. The place of the interpolator in Sigma-Delta DACs is briefly discussed. The summarized structure of the most common interpolators is presented. More applicable structures of interpolators were suggested and analyzed, providing the comparison with [1]. Having changed the structure of the incomplete interpolator and having optimized the stages, it was possible to improve the characteristic of amplitude frequency response with a smaller number of non-zero coefficients and much lower FPGA resources. The paper provides simulated results of the interpolator filter transmission characteristics as well as Sigma-Delta modulator quantization noise parameters. It is demonstrated that simulation of the complete converter system (interpolator + modulator + output filter) allows to identify places of the interpolator, where hardware resources could be saved, thereby reducing the chip area occupied by the converter, which is not always obvious when analyzing nodes separately. Therefore another version of the interpolator was proposed for the system ensuring larger suppression of the additional frequency band in the whole system compared with the previous interpolator. Simulated results related to occupied chip resources are also confirmed by the experiment, which was implemented in Xilinx Spartan FPGA.

A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Quantization Noise ◽  
Cmos Process ◽  
Noise Shaping ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

A 99.7-dB DR fourth-order sigma–delta modulator for digital gyroscope sensor

2017 ◽  
Vol 31 (09) ◽  
pp. 1750097 ◽  
Author(s):  
Xin-Peng Di ◽  
Wei-Ping Chen ◽  
Liang Yin ◽  
Xiao-Wei Liu
Keyword(s):  
Fourth Order ◽  
Dynamic Range ◽  
Low Frequency ◽  
Effective Area ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Interface Circuit ◽  
Transconductance Amplifier ◽  
Sample Frequency ◽  
Gyroscope Sensor

A fourth-order single-loop 1-bit sigma–delta [Formula: see text] modulator for digital gyroscope sensor interface circuit is presented in this paper. The effects caused by mismatch between parasite capacitors at the input of the operational transconductance amplifier (OTA) and the nonlinear on-resistance of the CMOS switch are analyzed. The chopping technique is adopted to eliminate the flick noise in low frequency. The modulator is fabricated in a standard CMOS 0.5-[Formula: see text] process and the effective area is 2 mm2. The power dissipation is 9.66 mW when the voltage is 5 V. The tested results show that a 93.7-dB peak signal-to-noise-and-distortion ratio (SNDR) and a 99.7-dB dynamic range (DR) are achievable at the sample frequency of 500 kHz for 2 kHz bandwidth. The optimization of the switches used in the first integrator and the parasite capacity is proved to be effective in the design of modulator.

The Design of the Integrator of Sigma-Delta Modulator

2013 ◽  
Vol 562-565 ◽  
pp. 477-481
Author(s):  
Xiao Wei Liu ◽  
Song Chen ◽  
Liang Liu ◽  
Jian Yang ◽  
Wei Ping Chen
Keyword(s):  
Low Frequency ◽  
Clock Signal ◽  
Gain Bandwidth ◽  
Two Phase ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Fully Differential ◽  
Unity Gain ◽  
Simulation Results ◽  
Sigma Delta Adc

A kind of fully differential integrator is designed for the modulator of Sigma-delta ADC in this paper. Fully differential structure is adopted to enlarge the amplitude of output, restrain nonlinearity and increase competence of anti-interference. The frequency of signal in this design is 10kHz and the frequency of clock signal is 100kHz. The design of fully differential integrator, capacitive common mode feedback, two-phase unoverlapping clock and switched capacitor integrator are accomplished in this paper. The simulation results in Cadence using 0.5um process show that the low-frequency gain of operational amplifier is 69.87dB, unity gain bandwidth is 37.74MHz, phase margin is 67.73 degrees and slew rate is more than 31V/μs.

A Novel Dual-Mode Low Pass Sigma-Delta Modulator Chip Design for WCDMA and Bluetooth Applications

2013 ◽  
Vol 660 ◽  
pp. 113-118
Author(s):  
Jhin Fang Huang ◽  
Wen Cheng Lai ◽  
Kun Jie Huang ◽  
Ron Yi Liu
Keyword(s):  
Supply Voltage ◽  
Cmos Process ◽  
Dual Mode ◽  
Chip Design ◽  
Loop Filter ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area ◽  
Low Pass ◽  
Σδ Modulator

A dual-mode low pass sigma-delta (ΣΔ) modulator at clock rates of 160 and 100 MHz respectively with cascaded integrators is presented for WCDMA and Bluetooth applications. One of main features is that cascaded integrators with feedback as well as distributed input coupling (CIFB) topology erase a summation amplifier and save power consumption. Another feature is that only one set loop filter is designed by switching capacitors to achieve a dual-mode function and greatly saves chip area. A prototype is fabricated in TSMC 0.18-m CMOS process. At the supply voltage of 1.8 V, measured results have achieved the SNDR of 42/33 dB over 1/2 MHz, respectively for Bluetooth/WCDMA. The chip dissipates a low power of 10.5 mW. Including pads the chip area is only 0.61 (0.71× 0.86) mm².

A digital low-frequency geophone based on 4th-order sigma-delta modulator and single-coil velocity feedback

2020 ◽  
Vol 312 ◽  
pp. 112074
Author(s):  
Xiaopeng Zhang ◽  
Xueyong Wei ◽  
Tongdong Wang ◽  
Xin Li ◽  
Weiguo Xiao ◽  
...  
Keyword(s):  
Low Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Velocity Feedback ◽  
Single Coil
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