Stress analysis in 3D IC having Thermal Through Silicon Vias (TTSV)

2013 ◽  
Author(s):  
Shabaz Basheer Patel ◽  
Tamal Ghosh ◽  
Asudeb Dutta ◽  
Shivgovind Singh
Keyword(s):  
Stress Analysis ◽  
3D Ic ◽  
Through Silicon Vias ◽  
Silicon Vias

Failure and Stress Analysis of Cu TSVs Using GHz-Scanning Acoustic Microscopy and Scanning Infrared Polariscopy

2015 ◽  
Author(s):  
Ingrid De Wolf ◽  
Ahmad Khaled ◽  
Martin Herms ◽  
Matthias Wagner ◽  
Tatjana Djuric ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Stress Analysis ◽  
Rayleigh Waves ◽  
Acoustic Microscopy ◽  
Scanning Acoustic Microscopy ◽  
Through Silicon Vias ◽  
Stress Anisotropy ◽  
Silicon Vias ◽  
Ic Technology ◽  
Detection Of Defects

Abstract This paper discusses the application of two different techniques for failure analysis of Cu through-silicon vias (TSVs), used in 3D stacked-IC technology. The first technique is GHz Scanning Acoustic Microscopy (GHz- SAM), which not only allows detection of defects like voids, cracks and delamination, but also the visualization of Rayleigh waves. GHz-SAM can provide information on voids, delamination and possibly stress near the TSVs. The second is a reflection-based photoelastic technique (SIREX), which is shown to be very sensitive to stress anisotropy in the Si near TSVs and as such also to any defect affecting this stress, such as delamination and large voids.

Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration

2011 ◽  
Vol 2011 (1) ◽  
pp. 000001-000007
Author(s):  
Chien-Ying Wu ◽  
Shang-Chun Chen ◽  
Pei-Jer Tzeng ◽  
John H. Lau ◽  
Yi-Feng Hsu ◽  
...  
Keyword(s):  
Cross Sections ◽  
3D Integration ◽  
Leakage Currents ◽  
3D Ic ◽  
Through Silicon Vias ◽  
Enabling Technologies ◽  
Key Enabling Technologies ◽  
Silicon Vias ◽  
Seed Layers

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu-plating of blind TSVs on 300mm wafers for 3D integration are investigated. Emphases are placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, leakage currents of the fabricated Cu-filled TSVs are measured. Furthermore cross sections and SEM of the fabricated TSVs are provided and examined.

RF Modeling of Through Silicon Vias (TSVs) in 3D IC

2010 ◽  
Author(s):  
C. W. Luo ◽  
Y. C. Wu ◽  
J. Y. Wang ◽  
S. S. H. Hsu
Keyword(s):  
3D Ic ◽  
Through Silicon Vias ◽  
Silicon Vias

High Frequency Signal Propagation in Through Silicon Vias

2012 ◽  
Vol 2012 (1) ◽  
pp. 000239-000243
Author(s):  
Srinidhi Raghavan Narasimhan ◽  
A. Ege Engin
Keyword(s):  
Wave Propagation ◽  
High Frequency ◽  
High Speed ◽  
Signal Propagation ◽  
Successful Implementation ◽  
High Frequency Signal ◽  
3D Ic ◽  
Through Silicon Vias ◽  
Integration Technology ◽  
Silicon Vias

The 3D IC integration technology and silicon interposers rely on through silicon vias (TSVs) for vertical interconnections. Hence, the medium carrying high frequency signals is lossy silicon (Si). Fundamental understanding of wave propagation through TSVs is essential for successful implementation of 3D IC integration technology as well as for the development of Si interposers at RF/microwave frequencies. The focus of this paper is characterization and modelling of TSVs and Si to explore high speed signal propagation through the lossy Si medium. To understand better the physical significance of the TSV, we will establish a framework for wave propagation through TSVs based on dielectric quasi-TEM, skin effect, and slow-wave modes similar to MIS micro-strip lines. For validation of the existence of these modes, full wave simulation results will be compared with simpler two dimensional transmission line simulators.

Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration

2012 ◽  
Vol 9 (1) ◽  
pp. 31-36 ◽  
Author(s):  
Chien-Ying Wu ◽  
Shang-Chun Chen ◽  
Pei-Jer Tzeng ◽  
John H. Lau ◽  
Yi-Feng Hsu ◽  
...  
Keyword(s):  
Leakage Current ◽  
Cross Sections ◽  
3D Integration ◽  
3D Ic ◽  
Through Silicon Vias ◽  
Enabling Technologies ◽  
Key Enabling Technologies ◽  
Silicon Vias ◽  
Seed Layers

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu plating of blind TSVs on 300 mm wafers for 3D integration are investigated. Emphasis is placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, the leakage current of the fabricated Cu-filled TSVs is measured. Furthermore, cross sections and SEM of the fabricated TSVs are examined.

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