A Novel Thin Wafer Handling Technology to Enable Cost-Effective Fabrication of Through-Glass Via Interposers

2014 ◽  
Vol 2014 (1) ◽  
pp. 000724-000728 ◽  
Author(s):  
Alvin Lee ◽  
Jay Su ◽  
Kim Arnold ◽  
Dongshun Bai ◽  
Bor Kai Wang ◽  
...  

Thin wafer handling technologies to fabricate silicon interposers have been widely discussed at conferences. Despite tremendous efforts to overcome several technical hurdles such as wafer chipping, cracking, and warpage, high manufacturing costs resulting from the complexity of the processes used to make silicon interposers remains a major concern. Fabricating a through-glass via (TGV) interposer using novel thin wafer handling (TWH) technology will be presented here as an example of a simple and cost-effective solution for realizing 2.5-D IC integration. Utilizing a simplified TWH technology, a TGV interposer with 30-μm-diameter vias to eliminate the isolation layer is combined with polymer-based polybenzoxazole (PBO) as passivation to build one to two redistribution layers (RDLs) with 20-μm line width on both sides after thinning to 100 μm. The simplified TWH requires only a release layer on the glass carrier and another layer of bonding material on the TGV wafer to enable fabrication of a TGV interposer. A process flow for fabricating a TGV interposer utilizing a simplified TWH technology will be presented in detail, including carrier treatment, bonding material, bonding, titanium/copper seed layer deposition, copper plating, RDL deposition, under-bump material (UBM) formation, debonding, and silicon chip stacking on a TGV interposer. The combination of TGV interposer and novel TWH technology will pave the way for cost-effective fabrication in 2.5-D IC.

2014 ◽  
Vol 556 ◽  
pp. 434-439 ◽  
Author(s):  
Jae-Min Park ◽  
Kwangseon Jin ◽  
Byeol Han ◽  
Myung Jun Kim ◽  
Jongwan Jung ◽  
...  

2011 ◽  
Vol 17 (1-3) ◽  
pp. 65-68 ◽  
Author(s):  
Sang-Woo Kang ◽  
Yong-Hyeon Shin ◽  
Jin-Tae Kim ◽  
Ju-Young Yun ◽  
Yun-Hee Chang ◽  
...  

Author(s):  
I. U. Abhulimen ◽  
T. Lam ◽  
A. Kamto ◽  
S. Burkett ◽  
L. Schaper ◽  
...  

Author(s):  
Dae-Yong Moon ◽  
Tae-Suk Kwon ◽  
Byung-Woo Kang ◽  
Woong-Sun Kim ◽  
Baek Mann Kim ◽  
...  

2005 ◽  
Vol 198 (1-3) ◽  
pp. 287-290 ◽  
Author(s):  
S.P. Chong ◽  
Y.C. Ee ◽  
Z. Chen ◽  
S.B. Law

2019 ◽  
Vol 35 (2) ◽  
pp. 125-132 ◽  
Author(s):  
Jiajun Mao ◽  
Eric Eisenbraun ◽  
Vincent Omarjee ◽  
Andrey Korolev ◽  
Christian Dussarrat

2003 ◽  
Vol 766 ◽  
Author(s):  
Vineet Sharma ◽  
Arief B. Suriadi ◽  
Frank Berauer ◽  
Laurie S. Mittelstadt

AbstractNormal photolithography tools have focal depth limitations and are unable to meet the expectations of high resolution photolithography on highly topographic structures. This paper shows a cost effective and promising technique of combining two different approaches to achieve critical dimensions of traces on slope pattern continuity on highly topographic structures. Electrophoretically deposited photoresist is used on 3-D structured wafers. This photoresist coating technique is fairly known in the MEMS industries to achieve uniform and conformal photoresist films on 3D surfaces. Multi step exposures are used to expose electrophoretically deposited photoresist. AlCu (Cu-0.5%), 0.47-0.53 μm thick metal film is deposited on 3D structured silicon substrate to plate photoresist. By combining these two novel methods, metal (AlCu) traces of 75 μm line width and 150 μm pitch (from top flat to down the slope) have been demonstrated on isotropically etched 350 μm deep trenches with 5-10% line width loss.


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