A Study on Sputtering of Copper Seed Layer for Interconnect Metallization via Molecular Dynamics Simulation

Interconnects are significant elements in integrated circuits (ICs), as they connect individual components of the circuit into a functioning whole. To form a void-free interconnect, a thin and uniform copper seed layer must be deposited as a basis for electroplating. In this paper, process parameters of sputtering including incident energy, incident angle, substrate temperature, and deposition rate were studied to form a uniform copper seed layer. Different liner/barrier materials and properties including crystal planes were also studied to enhance the quality of the copper seed layer. The study was carried out by molecular dynamics simulation. It revealed that increasing the incident energy and substrate temperature during the sputtering process increases their diffusivity but results in poorer uniformity and larger alloy percentage. By decreasing the deposition rate, the Ostwald ripening effect becomes dominant and increases the uniformity. An adequate incident angle could increase necking and uniformity. Among the sputtering process parameters and material properties discussed in this study, surface diffusion barrier energy of different crystal planes is the most decisive factor, which leads to good uniformity.

MOCVD Copper Metallization for High Aspect Ratios TSV 3D Integration.

MOCVD (Metal-Organic Chemical Vapor Deposition) copper metallization was developed on 300mm wafers, to fulfil 3D Through-Silicon Via (TSV) interconnect requirements. Using a fluorine-free organometallic precursor, the bis(dimethylamino-2-propoxy)copper (II) Cu[OCHMeCH2NMe2]2 at low temperature deposition, we developed a high purity, low stress copper film with strong adhesion to a TiN barrier layer. Argon was used as a carrier gas and H2 and/or H2O as a co-reactant. This MOCVD technique offers good conformality observed with 10μm×120μmTSVs. The thin copper seed layer was successfully integrated on 300mm wafers. A new XRD protocol was developed to characterize the copper seed layer along the TSV sidewalls, revealed higher microstructure quality, lower stressed in the case of copper film deposited by CVD compared to those deposited by i-PVD.

Enabling a Robust Copper Seed Etch Process for Fine Line RDL by Electroplating on a Thin PVD Seed Layer

Integration of heterogeneous chips into fanout packages requires interconnection by redistribution lines (RDL). As I/O counts increase, higher density routing is required, and can be achieved by finer RDL line/space dimension, stacking multiple RDL layers, or both. Conventional WLP plating processes for pillar or RDL use a PVD deposited copper seed layer between 1000 and 4000Å thick. Removal of this copper seed layer by isotropic wet etching leads to sidewall loss that can be ignored on larger features, but can lead to significant copper cross sectional area loss on features with 2/2μm line/space and below. By enabling plating onto much thinner seed layers, next generation WLP plating chambers enable a conventional copper seed layer etch process with less sidewall loss and more uniform cross-sectional area across plated features.

Using a Metal Oxide Adhesion Layer and Wet Chemical Cu Metallization for Fine Line Pattern Formation on Glass

With the trends towards miniaturization and heterogeneous integration, both IC and advanced substrate manufacturers are striving to meet the needs of next generation platforms, to increase the density of interconnects, and generate conductors featuring finer lines and spaces. Advanced manufacturing technologies such as Semi-Additive-Processing (SAP) and Advanced Modified-Semi-Additive-Processing (amSAP) were devised, realized and implemented in order to meet these requirements. Line and space (L/S) requirements of copper conductors will be below 5/5μm for advanced substrates, with 2/2μm L/S required for chip to chip connections in the near future. Herein we report about the performance of the new developed ferric sulfate based EcoFlash™ process for SAP and amSAP application with the focus on glass as the substrate and VitroCoat as thin metal oxide adhesion promotion layer. The adhesion promotion layer (about 5–10 nm thickness) is dip-coated by a modified sol-gel process followed by sintering which creates chemical bonds to the glass. The sol-gel dip coating process offers good coating uniformity on both Though-Glass-Via (TGV) and glass surfaces under optimized coating conditions. Uniform coating can be achieved up to aspect ratios of 10:1 by using a 300μm thick glass with 30μm diameter TGV. The thin adhesive layer enables electroless and electrolytic copper plating directly onto glass substrates. Excellent adhesion of electroless plated copper seed layer on glass can be achieved by using the adhesive layer and annealing technology. The thin adhesive layer is non-conductive and can be easily removed from the area between circuit traces together with the electroless copper seed layer by etching with a ferric sulfate based process. We have successfully integrated the adhesion layer and electroless and electrolytic copper plating technologies into semi-additive process and seed layer etching capable producing L/S below 10 μm.

First Demonstration of Fine Line RDL Yield Enhancement using an Innovative Ozone Treatment Process for Panel Fan-out and Interposers

As front end transistor scaling by Moore's law faces economic and technical challenges, interconnect scaling by advanced packaging technologies has started to add value at system level for a variety of electronics applications including consumer, high performance computing and automotive. The focus on yield improvement at every node that has enabled transistor scaling is now becoming a very critical need for high volume manufacturing of advanced packaging technologies such as 2.5D interposers and high density fanout [1]. This paper describes the first demonstration of a novel atmospheric approach based on ozone as an alternative to vacuum-based plasma treatment for photoresist cleaning to enhance the re-distribution layer (RDL) yields in advanced semi-additive process (SAP) processes. The ozone process is applicable to wafers as well as large panels, and is suited for small feature sizes down to 1um that are required for interposers and future fan-out packages. Ozone process provides an environmentally friendly solution eliminating the need for hazardous chemicals used in wet cleaning processes and has the potential to significantly increase throughput and reduce process cost compared to plasma processing by eliminating the need for vacuum chambers. The goal of this research is to demonstrate the effectiveness and benefits of the atmospheric dry ozone process developed using an MKS Instruments ozone delivery system for electrolytic copper plating yield improvement and dry film resist (DFR) residue cleaning, for 1-10um RDL critical dimensions (CD). The paper will describe the process fundamentals and the manufacturing tools, and discuss the characterization by contact angle measurements to confirm wettability of the plating surfaces, as well as demonstrate improvement of fine line RDL plating quality. The ever-increasing requirement for higher computing power in both high power applications and low power hand held or wearable devices is driving the need for higher signal bandwidth connections between logic and memory chips enabled through advances in the packaging world. The wiring density and I/O pitch are scaled down to achieve high bandwidth interconnections on a package with limited routing space. Photolithography, electrolytic copper plating, and copper seed layer etch are three crucial defining the yield and minimum feature size of RDL in the SAP flow. With the feature size scaling down to 3 μm, the quality of the metallized copper structure is crucial for high performance applications. Traditionally, wet chemical cleans are used for improving copper plating yields. The wet chemical process uses hazardous chemicals such as trichloroethylene (TCE) that are not environmentally friendly. These processes may be substituted with an oxygen plasma treatment that can clean organic residues in DFR trenches and improve wettability of the seed layers prior to plating as well as DFR residues after copper plating and DFR stripping. However, such plasma treatment approach requires a vacuum chamber which limits its throughput and cost effectiveness for high volume manufacturing. This paper proposes a higher throughput alternative solution to the plasma treatment process for electrolytic copper plating. Since the ozone gas is generated from oxygen, and reduced to oxygen upon process completion, no hazardous gas is required, or discharged into the atmosphere. To demonstrate the applicability of the ozone treatment to wafer-scale and panel-scale processing, two different types of copper seed layers, physical vapor deposition (PVD) Ti-Cu, and electroless plated copper, were evaluated. The effectiveness of both ozone and oxygen plasma treatments were qualified against a control sample with no treatment. The 7 μm thick DFR was laminated on the copper seed layers, then patterned with a projection lithography tool, and a minimum feature size of 3 μm was resolved. After photolithography, the substrates were subjected to ozone or plasma treatments. The water contact angle measurements show significant wettability improvement on the surfaces of substrates with copper seed layer, DFR, and DFR mesh patterned on a copper seed layer. Copper plating quality was then compared between samples. Both the ozone and plasma treatments resulted in excellent copper metallization quality due to the creation of a hydrophilic surface. The effectiveness of the ozone treatment at 50 deg C was confirmed, thus minimizing any impact on DFR stripping. The ozone treatment was also applied to clean the DFR residues after resist stripping and our results confirmed that the ozone process removed any remaining photoresist residues from the copper surface. In conclusion, this paper proposed and demonstrated high throughput, atmospheric pressure ozone treatment as an innovative alternative to plasma treatment for cleaning the surfaces prior to electrolytic copper plating, as well as for photoresist residue removal after resist strip. The results show yield improvement of plated RDL and DFR residue cleaning. The ozone process does not use any hazardous chemicals or gases and also does not require any vacuum steps, which makes it environmental friendly and high throughput, and offers a promising approach for fine line RDL for interposers and fan-out packages in meeting the semiconductor industry roadmap needs.

A Novel Thin Wafer Handling Technology to Enable Cost-Effective Fabrication of Through-Glass Via Interposers

Thin wafer handling technologies to fabricate silicon interposers have been widely discussed at conferences. Despite tremendous efforts to overcome several technical hurdles such as wafer chipping, cracking, and warpage, high manufacturing costs resulting from the complexity of the processes used to make silicon interposers remains a major concern. Fabricating a through-glass via (TGV) interposer using novel thin wafer handling (TWH) technology will be presented here as an example of a simple and cost-effective solution for realizing 2.5-D IC integration. Utilizing a simplified TWH technology, a TGV interposer with 30-μm-diameter vias to eliminate the isolation layer is combined with polymer-based polybenzoxazole (PBO) as passivation to build one to two redistribution layers (RDLs) with 20-μm line width on both sides after thinning to 100 μm. The simplified TWH requires only a release layer on the glass carrier and another layer of bonding material on the TGV wafer to enable fabrication of a TGV interposer. A process flow for fabricating a TGV interposer utilizing a simplified TWH technology will be presented in detail, including carrier treatment, bonding material, bonding, titanium/copper seed layer deposition, copper plating, RDL deposition, under-bump material (UBM) formation, debonding, and silicon chip stacking on a TGV interposer. The combination of TGV interposer and novel TWH technology will pave the way for cost-effective fabrication in 2.5-D IC.