scholarly journals VELAN: Variable Energy Aware Sense Amplifier Link for Asynchronous Network on Chip

2016 ◽  
Vol 07 (03) ◽  
pp. 128-144 ◽  
Author(s):  
Erulappan Sakthivel ◽  
Veluchamy Malathi ◽  
Muruganantham Arunraja
Keyword(s):  
Network On Chip ◽  
Energy Aware ◽  
Sense Amplifier ◽  
Asynchronous Network ◽  
On Chip ◽  
Variable Energy

scholarly journals MAS: Maximum Energy-Aware Sense Amplifier Link for Asynchronous Network on Chip

2021 ◽  
Author(s):  
Erulappan Sakthivel ◽  
Rengaraj Madavan
Keyword(s):  
Maximum Energy ◽  
Network On Chip ◽  
Energy Aware ◽  
Traffic Condition ◽  
Flip Flop ◽  
Power Pulse ◽  
Sense Amplifier ◽  
Asynchronous Network ◽  
Sense Amplifiers ◽  
On Chip

A real-time multiprocessor chip model is also called a Network-on-Chip (NoC), and deals a promising architecture for future systems-on-chips. Even though a lot of Double Tail Sense Amplifiers are used in architectural approach, the existing DTSA with transceiver exhibits a difficulty of consuming more energy than its gouged design during various traffic condition. Novel Low Power pulse Triggered Flip Flop with DTSA is designed in this research to eliminate the difficulty. The Traffic Aware Sense amplifier MAS consists of Sense amplifiers (SA’s), Traffic Generator, and Estimator. Among various SA’S suitable (DTSA and NLPTF -DTSA) SA are selected and information transferred to the receiver. The performance of both DTSA with Transceiver and NLPTF-DTSA with transceiver compared under various traffic conditions. The proposed design (NLPTF-DTSA) is observed on TSMC 90 nm technology, showing 5.92 Gb/s data rate and 0.51 W total link power.

Investigation of transient fault effects in synchronous and asynchronous Network on Chip router

2011 ◽  
Vol 57 (1) ◽  
pp. 61-68 ◽  
Author(s):  
Pooria M. Yaghini ◽  
Ashkan Eghbal ◽  
Hossein Pedram ◽  
Hamid Reza Zarandi
Keyword(s):  
Network On Chip ◽  
Transient Fault ◽  
Asynchronous Network ◽  
On Chip

Power analysis for asynchronous network-on-chip

2013 ◽  
Vol 8 (S1) ◽  
pp. S72-S80
Author(s):  
Mohamed A. Abd El Ghany ◽  
Gursharan Reehal ◽  
Mohammed Ismail
Keyword(s):  
Power Analysis ◽  
Network On Chip ◽  
Asynchronous Network ◽  
On Chip

Exploration of a scalable and power-efficient asynchronous Network-on-Chip with dynamic resource allocation

2018 ◽  
Vol 60 ◽  
pp. 173-184
Author(s):  
Charles Effiong ◽  
Gilles Sassatelli ◽  
Abdoulaye Gamatie
Keyword(s):  
Resource Allocation ◽  
Network On Chip ◽  
Dynamic Resource Allocation ◽  
Power Efficient ◽  
Asynchronous Network ◽  
Dynamic Resource ◽  
On Chip

Network on Chip for Consumer Electronics Devices: An Architectural and Performance Exploration of Synchronous and Asynchronous Network-on-Chip-Based Systems

2019 ◽  
Vol 8 (3) ◽  
pp. 50-54 ◽  
Author(s):  
Ayas Kanta Swain ◽  
Anil Kumar Rajput ◽  
Kamala Kanta Mahapatra
Keyword(s):  
Network On Chip ◽  
Consumer Electronics ◽  
Asynchronous Network ◽  
And Performance ◽  
On Chip

scholarly journals An architectural co-synthesis algorithm for energy-aware network-on-chip design

2007 ◽  
Author(s):  
Wei-Hsuan Hung ◽  
Yi-Jung Chen ◽  
Chia-Lin Yang ◽  
Yen-Sheng Chang ◽  
Alan P. Su
Keyword(s):  
Network On Chip ◽  
Energy Aware ◽  
Chip Design ◽  
Synthesis Algorithm ◽  
On Chip

Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application

2009 ◽  
Vol 3 (5) ◽  
pp. 487 ◽  
Author(s):  
X.-T. Tran ◽  
Y. Thonnart ◽  
J. Durupt ◽  
V. Beroulle ◽  
C. Robach
Keyword(s):  
Test Pattern ◽  
Network On Chip ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Design For Test ◽  
Asynchronous Network ◽  
On Chip
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