Linearity and Analog Performance Analysis of Double Gate Tunnel FET: Effect of Temperature and Gate Stack

Rakhi Narang;  Manoj Saxena;  Gupta;  Mridula Gupta

doi:10.5121/vlsic.2011.2316

Linearity and Analog Performance Analysis of Double Gate Tunnel FET: Effect of Temperature and Gate Stack

International Journal of VLSI Design & Communication Systems ◽

10.5121/vlsic.2011.2316 ◽

2011 ◽

Vol 2 (3) ◽

pp. 185-200 ◽

Cited By ~ 15

Author(s):

Rakhi Narang ◽

Manoj Saxena ◽

Gupta ◽

Mridula Gupta

Keyword(s):

Performance Analysis ◽

Effect Of Temperature ◽

Double Gate ◽

Gate Stack ◽

Tunnel Fet ◽

Analog Performance

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Effect of Temperature and Gate Stack on the Linearity and Analog Performance of Double Gate Tunnel FET

Trends in Network and Communications - Communications in Computer and Information Science ◽

10.1007/978-3-642-22543-7_47 ◽

2011 ◽

pp. 466-475 ◽

Cited By ~ 2

Author(s):

Rakhi Narang ◽

Manoj Saxena ◽

R. S. Gupta ◽

Mridula Gupta

Keyword(s):

Effect Of Temperature ◽

Double Gate ◽

Gate Stack ◽

Tunnel Fet ◽

Analog Performance

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Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET

20th International Symposium on Quality Electronic Design (ISQED) ◽

10.1109/isqed.2019.8697625 ◽

2019 ◽

Author(s):

Hung-Han Lin ◽

Vita Pi-Ho Hu

Keyword(s):

Performance Analysis ◽

Negative Capacitance ◽

Tunnel Fet ◽

Analog Performance

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Modelling and performance analysis of asymmetric double gate stack-oxide junctionless FET in subthreshold region

2017 IEEE Region 10 Humanitarian Technology Conference (R10-HTC) ◽

10.1109/r10-htc.2017.8289017 ◽

2017 ◽

Author(s):

Md. Shafiqul Islam ◽

Jannatul Afza ◽

Sanjida Tarannum

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Gate Stack ◽

Subthreshold Region ◽

And Performance

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An Analysis of Analog Performance for High-K Gate Stack Dielectric Pocket Double-Gate-All-Around (DP-DGAA) MOSFET

Lecture Notes in Electrical Engineering - Recent Trends in Electronics and Communication ◽

10.1007/978-981-16-2761-3_6 ◽

2021 ◽

pp. 71-78

Author(s):

Vaibhav Purwar ◽

Rajeev Gupta ◽

Nitish Kumar ◽

Himanshi Awasthi ◽

Rakesh Kumar Pandey

Keyword(s):

Double Gate ◽

Gate Stack ◽

High K ◽

Analog Performance

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Performance Analysis of High-κ Material Gate Stack Based Nanoscale Junction Less Double Gate MOSFET

Materials Focus ◽

10.1166/mat.2018.1505 ◽

2018 ◽

Vol 7 (2) ◽

pp. 259-267 ◽

Cited By ~ 8

Author(s):

Gaurav Dhiman ◽

Rajeev Pourush ◽

P. K. Ghosh

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Gate Stack ◽

Double Gate Mosfet

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Effect of temperature on analog performance of Mg2Si source heterojunction double gate tunnel field effect transistor

Materials Today Proceedings ◽

10.1016/j.matpr.2020.04.834 ◽

2020 ◽

Vol 28 ◽

pp. 1520-1524

Author(s):

Minaxi Dassi ◽

Jaya Madan ◽

Rahul Pandey ◽

Rajnish Sharma

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Effect Of Temperature ◽

Double Gate ◽

Analog Performance ◽

Effect Transistor ◽

Tunnel Field Effect Transistor

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Effect of dielectric constant and oxide thickness on the performance analysis of symmetric double gate stack-oxide junctionless field effect transistor in subthreshold region

2017 International Conference on Electrical, Computer and Communication Engineering (ECCE) ◽

10.1109/ecace.2017.7912895 ◽

2017 ◽

Cited By ~ 2

Author(s):

Chmmoy Nath Saha ◽

Raisa Fabiha ◽

Md. Shafiqul Islam

Keyword(s):

Dielectric Constant ◽

Performance Analysis ◽

Field Effect ◽

Field Effect Transistor ◽

Oxide Thickness ◽

Double Gate ◽

Gate Stack ◽

Subthreshold Region ◽

Effect Transistor

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Analytical modeling and performance analysis for symmetric double gate stack-oxide junctionless field effect transistor in subthreshold region

2017 IEEE Region 10 Humanitarian Technology Conference (R10-HTC) ◽

10.1109/r10-htc.2017.8288963 ◽

2017 ◽

Cited By ~ 2

Author(s):

Raisa Fabiha ◽

Chinmoy Nath Saha ◽

Md. Shafiqul Islam

Keyword(s):

Performance Analysis ◽

Field Effect ◽

Analytical Modeling ◽

Field Effect Transistor ◽

Double Gate ◽

Gate Stack ◽

Subthreshold Region ◽

Effect Transistor ◽

And Performance

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Performance Analysis of Nanoscale Double Gate MOSFETs with High-κ Gate Stack

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.110-116.1892 ◽

2011 ◽

Vol 110-116 ◽

pp. 1892-1899 ◽

Cited By ~ 1

Author(s):

Esmat Farzana ◽

Shuvro Chowdhury ◽

Rizvi Ahmed ◽

M. Ziaur Rahman Khan

Keyword(s):

Threshold Voltage ◽

Transport Model ◽

Ballistic Transport ◽

Drain Current ◽

Effect Of Temperature ◽

Double Gate ◽

Gate Stack ◽

Improved Performance ◽

High Dielectric

The performance and characteristics of Double Gate MOSFET with high dielectric constant (high-κ) gate stack have been analyzed and compared with those of conventional pure SiO2gate MOSFET. Quantum Ballistic Transport Model has been used to demonstrate the performance of the device in terms of threshold voltage, drain current in both low and high drain voltage regions and subthreshold swing. The effect of temperature on the threshold voltage and subthreshold characteristics has also been observed. This work reveals that improved performance of this structure can be achieved by scaling the gate length and illustrates its superiority over SiO2gate MOSFETs in achieving long-term ITRS goals.

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Simulation based Performance Analysis of a Double Gate Work Function Engineered Doped Tunnel FET

2018 IEEE Electron Devices Kolkata Conference (EDKCON) ◽

10.1109/edkcon.2018.8770435 ◽

2018 ◽

Author(s):

Supratim Subhra Das

Keyword(s):

Performance Analysis ◽

Work Function ◽

Double Gate ◽

Tunnel Fet ◽

Simulation Based ◽

Gate Work Function

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