scholarly journals A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage of Faulty Nodes, Not Always Detour

2020 ◽  
Author(s):  
Masaru Fukushi ◽  
Yota Kurokawa
Keyword(s):  
Fault Tolerant ◽  
Routing Algorithm ◽  
Slight Modification ◽  
Routing Algorithms ◽  
Future Research ◽  
Communication Performance ◽  
Novel Approach ◽  
Average Latency ◽  
The Common ◽  
On Chip

Due to the faults in system fabrication and run time, designing an efficient fault-tolerant routing algorithm with the property of deadlock-freeness is crucial for realizing dependable Network-on-Chip (NoC) systems with high communication performance. In this chapter, we introduce a novel approach for the design of fault-tolerant routing algorithms in NoCs. The common idea of the fault-tolerant routing has been undoubtedly to detour faulty nodes, while our approach allows passing through faulty nodes with the slight modification of NoC architecture. As a design example, we present an XY-based routing algorithm with the passage function. To investigate the effect of the approach, we compare the communication performance (i.e. average latency) of the XY-based algorithm with well-known region-based algorithms under the condition of with and without virtual channels. Finally, we provide possible directions of future research on the fault-tolerant routing with the passage function.

A New Fault Tolerant Routing Algorithm for Networks on Chip

2019 ◽  
Vol 10 (3) ◽  
pp. 68-85
Author(s):  
Chakib Nehnouh ◽  
Mohamed Senouci
Keyword(s):  
Network Architecture ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
Transient Faults ◽  
Networks On Chip ◽  
Congestion Detection ◽  
Novel Approach ◽  
On Chip ◽  
Detection Mechanisms ◽  
Correct Data

To provide correct data transmission and to handle the communication requirements, the routing algorithm should find a new path to steer packets from the source to the destination in a faulty network. Many solutions have been proposed to overcome faults in network-on-chips (NoCs). This article introduces a new fault-tolerant routing algorithm, to tolerate permanent and transient faults in NoCs. This solution called DINRA can satisfy simultaneously congestion avoidance and fault tolerance. In this work, a novel approach inspired by Catnap is proposed for NoCs using local and global congestion detection mechanisms with a hierarchical sub-network architecture. The evaluation (on reliability, latency and throughput) shows the effectiveness of this approach to improve the NoC performances compared to state of art. In addition, with the test module and fault register integrated in the basic architecture, the routers are able to detect faults dynamically and re-route packets to fault-free and congestion-free zones.

A Fault-Tolerant Routing Algorithm Using Tunnels in Fault Blocks for Network-on-Chip

2017 ◽  
Vol 27 (02) ◽  
pp. 1850022 ◽  
Author(s):  
Ling Wang ◽  
Terrence Mak
Keyword(s):  
Fault Tolerant ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Mesh Network ◽  
Communication Performance ◽  
Simulation Results ◽  
On Chip

In 2D mesh Network on Chips (NoCs), fault-tolerant algorithms usually deactivate healthy nodes to form rectangular or convex fault blocks. However, the deactivated nodes can possibly form an available tunnel in a faulty block. We propose a method to discover these tunnels, and propose a fault-tolerant routing algorithm to route messages through such paths such that the overall communication performance is improved. In addition, the algorithm is deadlock-free by prohibiting some turns. Simulation results demonstrate that the reuse of the sacrificed nodes in fault blocks can significantly reduce the average message latency.

Double Stairs: A Fault-Tolerant Routing Algorithm for Networks-on-Chip

2016 ◽  
Vol 25 (06) ◽  
pp. 1650065 ◽  
Author(s):  
Saleh Fakhrali ◽  
Hamid R. Zarandi
Keyword(s):  
Fault Tolerance ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
Deep Submicron ◽  
Routing Algorithms ◽  
Experimental Results ◽  
Trade Off ◽  
Networks On Chip ◽  
On Chip ◽  
Probabilistic Flooding

Reliability is one of the main concerns in the design of networks-on-chip (NoCs) due to the use of deep submicron technologies in fabrication of such products. This paper presents a new fault-tolerant routing algorithm called double stairs for NoCs. Double stairs routing algorithm is a low overhead routing that has the ability to deal with fault. The proposed routing algorithm makes a redundant copy of each packet at the source node and routes the original and redundant packets in a new partially adaptive routing algorithm. The method is evaluated for various packet injection rates and fault rates. Experimental results show that the proposed routing algorithm offers the best trade-off between performance and fault tolerance compared to other routing algorithms, namely flooding, XYX and probabilistic flooding.

Latency, Throughput and Power Aware Adaptive NoC Routing on Orthogonal Convex Faulty Region

2019 ◽  
Vol 28 (04) ◽  
pp. 1950055 ◽  
Author(s):  
Munshi Mostafijur Rahaman ◽  
Prasun Ghosal ◽  
Tuhin Subhra Das
Keyword(s):  
Performance Enhancement ◽  
Fault Tolerant ◽  
Routing Algorithms ◽  
Communication Process ◽  
Block Boundary ◽  
Fault Block ◽  
Average Latency ◽  
Virtual Boundary ◽  
And Performance ◽  
On Chip

Reliability of a Network-on-Chip (NoC) relies vastly upon the efficiency of handling faults. Faults those lead to trouble during on-chip communication process are basically of two types namely soft and hard. Here, hard faults are considered. Hard faults may be caused due to failure of links, routers, or other processing units. These are mainly dealt with fault-tolerant routing algorithms or by employing redundant hardware. Multiple faulty nodes are being avoided by acquiring region-based approaches. Most of the fault-tolerant routing techniques are designed on homogeneous faulty regions where some active nodes also act as deactivated nodes to build the region homogeneous. On the other hand, adaptive routing on nonhomogeneous faulty regions increases load on its boundary and most of them does not assure deadlock freeness. This paper proposes a deadlock-free adaptive fault-tolerant NoC routing named F-Route-NoC-Mesh (FRNM) ignoring any virtual channel on orthogonal convex faulty regions. Contributions of this work focus on balancing network traffic by assuming a virtual faulty block boundary and routing packets through this virtual boundary. Destination does not exist within that virtual faulty block regions to reduce load on the boundary of orthogonal faulty regions. Thus, this work is aimed at acquiring proper incorporation of procedures being able to reach fault-tolerant degree, routing efficiency and performance enhancement. Using the proposed algorithm (FRNM), a fault block model-based approach is developed. Significant improvements of average latency (43.37% to 60.44%), average throughput (4.18% to 90.81%) and power consumption (5.93% to 33.28%) are achieved over the state-of-the-art by using a cycle accurate simulator.

A Novel Adaptive Routing Algorithm for Network-On-Chip

2011 ◽  
Vol 474-476 ◽  
pp. 413-416
Author(s):  
Jia Jia ◽  
Duan Zhou ◽  
Jian Xian Zhang
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Experimental Results ◽  
Average Latency ◽  
On Chip

In this paper, we propose a novel adaptive routing algorithm to solve the communication congestion problem for Network-on-Chip (NoC). The strategy competing for output ports in both X and Y directions is employed to utilize the output ports of the router sufficiently, and to reduce the transmission latency and improve the throughput. Experimental results show that the proposed algorithm is very effective in relieving the communication congestion, and a reduction in average latency by 45.7% and an improvement in throughput by 44.4% are achieved compared with the deterministic XY routing algorithm and the simple XY adaptive routing algorithm.

Comparative Performance Analysis of 
Selected Routing Algorithms by Load Variation of 2-Dimensional Mesh Topology Based 
Network-On-Chip

2021 ◽  
Vol 20 (3) ◽  
pp. 1-6
Author(s):  
Mohammed Shaba Saliu ◽  
Muyideen Omuya Momoh ◽  
Pascal Uchenna Chinedu ◽  
Wilson Nwankwo ◽  
Aliu Daniel
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Injection Rate ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Comparative Performance ◽  
Traffic Pattern ◽  
Mesh Topology ◽  
Similar Vein ◽  
On Chip

Network-on-Chip (NoC) has been proposed as a viable solution to the communication challenges on System-on-Chips (SoCs). As the communication paradigm of SoC, NoCs performance depends mainly on the type of routing algorithm chosen. In this paper different categories of routing algorithms were compared. These include XY routing, OE turn model adaptive routing, DyAD routing and Age-Aware adaptive routing.  By varying the load at different Packet Injection Rate (PIR) under random traffic pattern, comparison was conducted using a 4 × 4 mesh topology. The Noxim simulator, a cycle accurate systemC based simulator was employed. The packets were modeled as a Poisson distribution; first-in-first-out (FIFO) input buffer channel with a depth of five (5) flits and a flit size of 32 bits; and a packet size of 3 flits respectively. The simulation time was 10,000 cycles. The findings showed that the XY routing algorithm performed better when the PIR is low.  In a similar vein, the DyAD routing and Age-aware algorithms performed better when the load i.e. PIR is high.

scholarly journals A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1076 ◽  
Author(s):  
Zulqar Nain ◽  
Rashid Ali ◽  
Sheraz Anjum ◽  
Muhammad Khalil Afzal ◽  
Sung Won Kim
Keyword(s):  
Fault Tolerant ◽  
Current System ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Traffic Load ◽  
Delivery Ratio ◽  
Processing Elements ◽  
System On A Chip ◽  
On Chip ◽  
Network On A Chip

Scalability is a significant issue in system-on-a-chip architectures because of the rapid increase in numerous on-chip resources. Moreover, hybrid processing elements demand diverse communication requirements, which system-on-a-chip architectures are unable to handle gracefully. Network-on-a-chip architectures have been proposed to address the scalability, contention, reusability, and congestion-related problems of current system-on-a-chip architectures. The reliability appears to be a challenging aspect of network-on-a-chip architectures because of the physical faults introduced in post-manufacturing processes. Therefore, to overcome such failures in network-on-a-chip architectures, fault-tolerant routing is critical. In this article, a network adaptive fault-tolerant routing algorithm is proposed, where the proposed algorithm enhances an efficient dynamic and adaptive routing algorithm. The proposed algorithm avoids livelocks because of its ability to select an alternate outport. It also manages to bypass congested regions of the network and balances the traffic load between outports that have an equal number of hop counts to its destination. Simulation results verified that in a fault-free scenario, the proposed solution outperformed a fault-tolerant XY by achieving a lower latency. At the same time, it attained a higher flit delivery ratio compared to the efficient dynamic and adaptive routing algorithm. Meanwhile, in the situation of a faulty network, the proposed algorithm could reach a higher flit delivery ratio of up to 18% while still consuming less power compared to the efficient dynamic and adaptive routing algorithm.

Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems

2017 ◽  
Vol 28 (3) ◽  
pp. 838-849 ◽  
Author(s):  
Yu-Yin Chen ◽  
En-Jui Chang ◽  
Hsien-Kai Hsin ◽  
Kun-Chih Chen ◽  
An-Yeu Andy Wu
Keyword(s):  
Fault Tolerant ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Path Diversity ◽  
On Chip
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