Transistor-level characterization of static random access memory bit failures induced by random telegraph noise

2016 ◽  
Vol 55 (4S) ◽  
pp. 04ED05 ◽  
Author(s):  
Tomoko Mizutani ◽  
Takuya Saraya ◽  
Kiyoshi Takeuchi ◽  
Masaharu Kobayashi ◽  
Toshiro Hiramoto
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Random Telegraph Noise ◽  
Telegraph Noise

Operations, Charge Transport, and Random Telegraph Noise in HfOx Resistive Random Access Memory: a Multi-scale Modeling Study

MRS Advances ◽  
2016 ◽  
Vol 1 (5) ◽  
pp. 327-338 ◽  
Author(s):  
Francesco M. Puglisi ◽  
Luca Larcher ◽  
Andrea Padovani ◽  
Paolo Pavan
Keyword(s):  
Charge Transport ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Operating Conditions ◽  
Current Fluctuations ◽  
Access Memory ◽  
Random Telegraph Noise ◽  
Multi Scale ◽  
Telegraph Noise

ABSTRACTIn this work we explore the mechanisms responsible for Random Telegraph Noise (RTN) fluctuations in HfOx Resistive Random Access Memory (RRAM) devices. The statistical properties of the RTN are analyzed in many operating conditions exploiting the Factorial Hidden Markov Model (FHMM) to decompose the multilevel RTN traces in a superposition of two-level fluctuations. This allows the simultaneous characterization of individual defects contributing to the RTN. Results, together with multi-scale physics-based simulations, allows thoroughly investigating the physical mechanisms which could be responsible for the RTN current fluctuations in the two resistive states of these devices, including also the charge transport features in a comprehensive framework. We consider two possible options, which are the Coulomb blockade effect and the possible existence of metastable states for the defects assisting charge transport. Results indicate that both options may be responsible for RTN current fluctuations in HRS, while RTN in LRS is attributed to the temporary screening effect of the charge trapped at defect sites around the conductive filament.

Anomalous random telegraph noise and temporary phenomena in resistive random access memory

2016 ◽  
Vol 125 ◽  
pp. 204-213 ◽  
Author(s):  
Francesco Maria Puglisi ◽  
Luca Larcher ◽  
Andrea Padovani ◽  
Paolo Pavan
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Access Memory ◽  
Random Telegraph Noise ◽  
Telegraph Noise

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

Challenges and Benefits of Product-Like SRAM in Technology Development

2011 ◽  
Author(s):  
Felix Beaudoin ◽  
Stephen Lucarini ◽  
Fred Towler ◽  
Stephen Wu ◽  
Zhigang Song ◽  
...  
Keyword(s):  
Technology Development ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Development Phase ◽  
High Complexity ◽  
Access Memory ◽  
Integration Schemes ◽  
Front End

Abstract For SRAMs with high logic complexity, hard defects, design debug, and soft defects have to be tackled all at once early on in the technology development while innovative integration schemes in front-end of the line are being validated. This paper presents a case study of a high-complexity static random access memory (SRAM) used during a 32nm technology development phase. The case study addresses several novel and unrelated fail mechanisms on a product-like SRAM. Corrective actions were put in place for several process levels in the back-end of the line, the middle of the line, and the front-end of the line. These process changes were successfully verified by demonstrating a significant reduction of the Vmax and Vmin nest array block fallout, thus allowing the broader development team to continue improving random defectivity.

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