Understanding the Impact of Process Variations on Analog Circuit Performance with Halo Channel Doped Deep Sub-Micron CMOS Technologies

2004 ◽  
Author(s):  
K. Narasimhulu ◽  
V. Ramgopal Rao
Keyword(s):  
Analog Circuit ◽  
Process Variations ◽  
Circuit Performance ◽  
The Impact

Evaluation of the Impact of Layout on Device and Analog Circuit Performance With Lateral Asymmetric Channel MOSFETs

2005 ◽  
Vol 52 (7) ◽  
pp. 1603-1609 ◽  
Author(s):  
D.V. Kumar ◽  
K. Narasimhulu ◽  
P.S. Reddy ◽  
M. Shojaei-Baghini ◽  
D.K. Sharma ◽  
...  
Keyword(s):  
Analog Circuit ◽  
Asymmetric Channel ◽  
Circuit Performance ◽  
The Impact

A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance

2010 ◽  
Vol 29 (4) ◽  
pp. 627-631 ◽  
Author(s):  
Rajesh A. Thakker ◽  
Chaitanya Sathe ◽  
Maryam Shojaei Baghini ◽  
Mahesh B. Patil
Keyword(s):  
Process Variations ◽  
Circuit Performance ◽  
The Impact

scholarly journals Gate Sizing Methodology with a Novel Accurate Metric to Improve Circuit Timing Performance under Process Variations

Technologies ◽  
2020 ◽  
Vol 8 (2) ◽  
pp. 25 ◽  
Author(s):  
Zahira Perez-Rivera ◽  
Esteban Tlelo-Cuautle ◽  
Victor Champac
Keyword(s):  
Standard Deviation ◽  
Integrated Circuits ◽  
Computing Time ◽  
Process Variations ◽  
Path Selection ◽  
Economic Losses ◽  
Gate Sizing ◽  
Circuit Performance ◽  
Average Percentage ◽  
The Impact

The impact of process variations on circuit performance has become more critical with the technological scaling, and the increasing level of integration of integrated circuits. The degradation of the performance of the circuit means economic losses. In this paper, we propose an efficient statistical gate-sizing methodology for improving circuit speed in the presence of independent intra-die process variations. A path selection method, a heuristic, two coarse selection metrics, and one fine selection metric are part of the new proposed methodology. The fine metric includes essential concepts like the derivative of the standard deviation of delay, a path segment analysis, the criticality, the slack-time, and area. The proposed new methodology is applied to ISCAS Benchmark circuits. The average percentage of optimization in the delay is 12%, the average percentage of optimization in the delay standard deviation is 27.8%, the average percentage in the area increase is less than 5%, and computing time is up to ten times less than using analytical methods like Lagrange Multipliers.

scholarly journals Process Variability—Technological Challenge and Design Issue for Nanoscale Devices

Micromachines ◽  
2018 ◽  
Vol 10 (1) ◽  
pp. 6 ◽  
Author(s):  
Jürgen Lorenz ◽  
Eberhard Bär ◽  
Sylvain Barraud ◽  
Andrew Brown ◽  
Peter Evanschitzky ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Process Variations ◽  
Electrical Performance ◽  
Process Equipment ◽  
Process Variability ◽  
Circuit Performance ◽  
Technological Challenge ◽  
Device Properties ◽  
The Impact ◽  
Full Simulation

Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization of the device geometries even more important, both in view of the nominal electrical performance to be achieved and its variations. In turn, it is essential to accurately simulate the device geometry and its impact on the device properties, including the effect caused by non-idealized processes which are subject to various kinds of systematic variations induced by process equipment. In this paper, the hierarchical simulation system developed in the SUPERAID7 project to study the impact of variations from equipment to circuit level is presented. The software system consists of a combination of existing commercial and newly developed tools. As the paper focuses on technological challenges, especially issues resulting from the structuring processes needed to generate the three-dimensional device architectures are discussed. The feasibility of a full simulation of the impact of relevant systematic and stochastic variations on advanced devices and circuits is demonstrated.

Predicting Analog Circuit Performance Based on Importance of Uncertainties

2010 ◽  
Vol E93-C (6) ◽  
pp. 893-904
Author(s):  
Jin SUN ◽  
Kiran POTLURI ◽  
Janet M. WANG
Keyword(s):  
Analog Circuit ◽  
Circuit Performance

Design of a Robust Memristive Spiking Neuromorphic System with Unsupervised Learning in Hardware

2021 ◽  
Vol 17 (4) ◽  
pp. 1-26
Author(s):  
Md Musabbir Adnan ◽  
Sagarvarma Sayyaparaju ◽  
Samuel D. Brown ◽  
Mst Shamim Ara Shawkat ◽  
Catherine D. Schuman ◽  
...  
Keyword(s):  
Unsupervised Learning ◽  
Recognition Task ◽  
Single Layer ◽  
Process Variations ◽  
Spike Timing ◽  
System Level ◽  
Design Parameters ◽  
Digital Pulse ◽  
Neuromorphic System ◽  
The Impact

Spiking neural networks (SNN) offer a power efficient, biologically plausible learning paradigm by encoding information into spikes. The discovery of the memristor has accelerated the progress of spiking neuromorphic systems, as the intrinsic plasticity of the device makes it an ideal candidate to mimic a biological synapse. Despite providing a nanoscale form factor, non-volatility, and low-power operation, memristors suffer from device-level non-idealities, which impact system-level performance. To address these issues, this article presents a memristive crossbar-based neuromorphic system using unsupervised learning with twin-memristor synapses, fully digital pulse width modulated spike-timing-dependent plasticity, and homeostasis neurons. The implemented single-layer SNN was applied to a pattern-recognition task of classifying handwritten-digits. The performance of the system was analyzed by varying design parameters such as number of training epochs, neurons, and capacitors. Furthermore, the impact of memristor device non-idealities, such as device-switching mismatch, aging, failure, and process variations, were investigated and the resilience of the proposed system was demonstrated.

Sign in / Sign up

Export Citation Format

Share Document