scholarly journals Gate Sizing Methodology with a Novel Accurate Metric to Improve Circuit Timing Performance under Process Variations

Technologies ◽  
2020 ◽  
Vol 8 (2) ◽  
pp. 25 ◽  
Author(s):  
Zahira Perez-Rivera ◽  
Esteban Tlelo-Cuautle ◽  
Victor Champac
Keyword(s):  
Standard Deviation ◽  
Integrated Circuits ◽  
Computing Time ◽  
Process Variations ◽  
Path Selection ◽  
Economic Losses ◽  
Gate Sizing ◽  
Circuit Performance ◽  
Average Percentage ◽  
The Impact

The impact of process variations on circuit performance has become more critical with the technological scaling, and the increasing level of integration of integrated circuits. The degradation of the performance of the circuit means economic losses. In this paper, we propose an efficient statistical gate-sizing methodology for improving circuit speed in the presence of independent intra-die process variations. A path selection method, a heuristic, two coarse selection metrics, and one fine selection metric are part of the new proposed methodology. The fine metric includes essential concepts like the derivative of the standard deviation of delay, a path segment analysis, the criticality, the slack-time, and area. The proposed new methodology is applied to ISCAS Benchmark circuits. The average percentage of optimization in the delay is 12%, the average percentage of optimization in the delay standard deviation is 27.8%, the average percentage in the area increase is less than 5%, and computing time is up to ten times less than using analytical methods like Lagrange Multipliers.

A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance

2010 ◽  
Vol 29 (4) ◽  
pp. 627-631 ◽  
Author(s):  
Rajesh A. Thakker ◽  
Chaitanya Sathe ◽  
Maryam Shojaei Baghini ◽  
Mahesh B. Patil
Keyword(s):  
Process Variations ◽  
Circuit Performance ◽  
The Impact

scholarly journals Improved fault tolerance of Turbo decoding based on optimized index assignments

2014 ◽  
Vol 12 ◽  
pp. 187-195 ◽  
Author(s):  
J. Geldmacher ◽  
J. Götze
Keyword(s):  
Integrated Circuits ◽  
Communication Systems ◽  
Fault Tolerant ◽  
Error Resilience ◽  
Process Variations ◽  
Design Of Algorithms ◽  
Turbo Decoder ◽  
Index Assignment ◽  
Reduced Power Consumption ◽  
The Impact

Abstract. This paper investigates the impact of an error-prone buffer memory on a channel decoder as employed in modern digital communication systems. On one hand this work is motivated by the fact that energy efficient decoder implementations may not only be achieved by optimizations on algorithmic level, but also by chip-level modifications. One of such modifications is so called aggressive voltage scaling of buffer memories, which, while achieving reduced power consumption, also injects errors into the likelihood values used during the decoding process. On the other hand, it has been recognized that the ongoing increase of integration density with smaller structures makes integrated circuits more sensitive to process variations during manufacturing, and to voltage and temperature variations. This may lead to a paradigm shift from 100 %-reliable operation to fault tolerant signal processing. Both reasons are the motivation to discuss the required co-design of algorithms and underlying circuits. For an error-prone receive buffer of a Turbo decoder the influence of quantizer design and index assignment on the error resilience of the decoding algorithm is discussed. It is shown that a suitable design of both enables a compensation of hardware induced bits errors with rates up to 1 % without increasing the computational complexity of the decoder.

Overview of High Performance Packaging Materials

1990 ◽  
Vol 203 ◽  
Author(s):  
Barry C. Johnson
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Building Blocks ◽  
Electrical Performance ◽  
Electronic Systems ◽  
Circuit Performance ◽  
Signal Velocity ◽  
Semiconductor Chip ◽  
Thermal Cooling ◽  
The Impact

ABSTRACTHigh Performance Integrated Circuits form the basic building blocks of modern electronic systems that are designed to process ever larger numbers of electrical signals at greater signal velocity and fidelity. In such applications, each circuit must be packaged in order to provide it with necessary mechanical support, environmental protection, electrical interconnection and thermal cooling. The package, however, can also impose certain constraints on the chip. It can degrade electrical performance, add size and weight, introduce reliability problems and increase cost. Thus, packaging can be viewed as a complex balance between the provision of desired functions and the reduction of associated constraints.The ability to strike a proper balance has become increasingly difficult in recent years due to the relentless march of integrated circuits toward higher levels of complexity, size, speed, heat flux and customization. It is anticipated that the continuing evolution of high performance circuits and systems will soon be limited by the package designs and materials-of-construction, rather than by the devices on the semiconductor chip.The intent of this talk is to provide a brief overview of high performance packaging and the related materials issues. The approach is to (a) present the forecasted trends in relevant circuit performance characteristics, (b) discuss the impact of these characteristics on current chip and board level packaging methods, and (c) present new package and materials concepts that might furnish potential solutions to the developing circuit-package performance gap.

scholarly journals Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1256
Author(s):  
Seyedehsomayeh Hatefinasab ◽  
Noel Rodriguez ◽  
Antonio García ◽  
Encarnacion Castillo
Keyword(s):  
Standard Deviation ◽  
Power Consumption ◽  
Threshold Voltage ◽  
Low Cost ◽  
Process Variations ◽  
Cmos Technology ◽  
Soft Error ◽  
Single Event ◽  
Power Delay Product ◽  
The Impact

In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%.

scholarly journals Process Variability—Technological Challenge and Design Issue for Nanoscale Devices

Micromachines ◽  
2018 ◽  
Vol 10 (1) ◽  
pp. 6 ◽  
Author(s):  
Jürgen Lorenz ◽  
Eberhard Bär ◽  
Sylvain Barraud ◽  
Andrew Brown ◽  
Peter Evanschitzky ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Process Variations ◽  
Electrical Performance ◽  
Process Equipment ◽  
Process Variability ◽  
Circuit Performance ◽  
Technological Challenge ◽  
Device Properties ◽  
The Impact ◽  
Full Simulation

Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization of the device geometries even more important, both in view of the nominal electrical performance to be achieved and its variations. In turn, it is essential to accurately simulate the device geometry and its impact on the device properties, including the effect caused by non-idealized processes which are subject to various kinds of systematic variations induced by process equipment. In this paper, the hierarchical simulation system developed in the SUPERAID7 project to study the impact of variations from equipment to circuit level is presented. The software system consists of a combination of existing commercial and newly developed tools. As the paper focuses on technological challenges, especially issues resulting from the structuring processes needed to generate the three-dimensional device architectures are discussed. The feasibility of a full simulation of the impact of relevant systematic and stochastic variations on advanced devices and circuits is demonstrated.

Backside Emission Microscopy for Integrated Circuits on Heavily Doped Substrate

1998 ◽  
Author(s):  
Ching-Lang Chiang ◽  
Neeraj Khurana ◽  
Daniel T. Hurley ◽  
Ken Teasdale
Keyword(s):  
Integrated Circuits ◽  
Ccd Camera ◽  
Preparation Technique ◽  
Absorption Data ◽  
Ir Radiation ◽  
Heavily Doped ◽  
Emission Microscopy ◽  
Diffraction Patterns ◽  
Emission Detection ◽  
The Impact

Abstract Backside emission microscopy on heavily doped substrate materials was analyzed from the viewpoint of optical absorption by the substrate and sample preparation technique. Although it was widely believed that silicon is transparent to infrared (IR) radiation, we demonstrated by using published absorption data that silicon with doping levels above 5 x 1018cm-3 is virtually opaque, leaving only a narrow transmission window around the energy bandgap. Because the transmission depends exponentially on the thickness of die, thinning to below 100µm is shown to be required. Even an advanced IR sensor such as HgCdTe would find little light to detect without thinning the die. For imaging the circuit, an IR laser-based system produced poor images in which the diffraction patterns often ruined the contrast and obscured the image. Hence, a precise, controlled die thinning technique is required both for emission detection and backside imaging. A thinning and polishing technique was briefly described that was believed to be applicable to most ceramic packages. A software technique was employed to solve the image quality problem commonly encountered in backside imaging applications using traditional microscope light source and a scientific grade CCD camera. Finally, we showed the impact of die thickness on imaging circuits on a heavily doped n type substrate.

An Overview of 300 mm SOI Starting Wafer Quality and Its Yield Detractors

2005 ◽  
Author(s):  
Pei Y. Tsai ◽  
Junedong Lee ◽  
Paul Ronsheim ◽  
Lindsay Burns ◽  
Richard Murphy ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Device Fabrication ◽  
Sampling Plan ◽  
Silicon On Insulator ◽  
Manufacturing Processes ◽  
Circuit Performance ◽  
Characterization Techniques ◽  
Wafer Manufacturing

Abstract A stringent sampling plan is developed to monitor and improve the quality of 300mm SOI (silicon on insulator) starting wafers procured from the suppliers. The ultimate goal is to obtain the defect free wafers for device fabrication and increase yield and circuit performance of the semiconductor integrated circuits. This paper presents various characterization techniques for QC monitor and examples of the typical defects attributed to wafer manufacturing processes.

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