Low Gate Charge Power VDMOSFETs with Dual-Gate Floating NP Well Design

2008 ◽  
Author(s):  
C. N. Liao ◽  
F. T. Chien ◽  
Y. T. Tsai
Keyword(s):  
2020 ◽  
Vol 126 (3) ◽  
Author(s):  
Ravi Ranjan ◽  
Nitesh Kashyap ◽  
Ashish Raman

2013 ◽  
Vol 34 (6) ◽  
pp. 756-758 ◽  
Author(s):  
Ki-Hyun Jang ◽  
Hyun-June Jang ◽  
Jin-Kwon Park ◽  
Won-Ju Cho

1978 ◽  
Vol 2 (6) ◽  
pp. 207 ◽  
Author(s):  
G.S. Hobson ◽  
R. Longstone ◽  
R.C. Tozer

2009 ◽  
Author(s):  
C. N. Liao ◽  
F. T. Chien ◽  
C. M. Lin ◽  
C. H. Ho ◽  
Y. T. Tsai
Keyword(s):  

1993 ◽  
Vol 3 (9) ◽  
pp. 1719-1728
Author(s):  
P. Dollfus ◽  
P. Hesto ◽  
S. Galdin ◽  
C. Brisset

Author(s):  
Cheng-Piao Lin ◽  
Chin-Hsin Tang ◽  
Cheng-Hsu Wu ◽  
Cheng-Chun Ting

Abstract This paper analyzes several SRAM failures using nano-probing technique. Three SRAM single bit failures with different kinds of Gox breakdown defects analyzed are gross function single bit failure, data retention single bit failure, and special data retention single bit failure. The electrical characteristics of discrete 6T-SRAM cells with soft breakdown are discussed and correlated to evidences obtained from physical analysis. The paper also verifies many previously published simulation data. It utilizes a 6T-SRAM vehicle consisting of a large number of SRAM cells fabricated by deep sub-micron, dual gate, and copper metallization processes. The data obtained from this paper indicates that Gox breakdown location within NMOS pull-down device has larger a impact on SRAM stability than magnitude of gate leakage current, which agrees with previously published simulation data.


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