VDS and VGS Depolarization Effect on SiC MOSFET Short-Circuit Withstand Capability Considering Partial Safe Failure-Mode

This paper presents a detailed analysis of 1200 V Silicon Carbide (SiC) power MOSFET exhibiting different short-circuit failure mechanisms and improvement in reliability by VDS and VGS depolarization. The device robustness has undergone an incremental pulse under different density decreasing; either drain-source voltage or gate-driver voltage. Unlike silicon device, the SiC MOSFET failure mechanism firstly displays specific gradual gate-cracks mechanism and progressive gate-damage accumulations greater than 4 µs/9 J·cm−2. Secondly, a classical drain-source thermal runaway appears, as for silicon devices, in a time greater than 9 µs. Correlations with short-circuit energy measurements and temperature simulations are investigated. It is shown that the first mechanism is an incremental soft gate-failure-mode which can be easily used to detect and protect the device by a direct feedback on the gate-driver. Furthermore, it is highlighted that this new mechanism can be sufficiently consolidated to avoid the second drain-source mechanism which is a hard-failure-mode. For this purpose, it is proposed to sufficiently depolarize the on-state gate-drive voltage to reduce the chip heating-rate and thus to decouple the failure modes. The device is much more robust with a short-circuit withstand time higher than 10 µs, as in silicon, no risk of thermal runaway and with an acceptable penalty on RDS-ON.

Preparation, Imaging, and Design Extraction of the Front-End-of-Line and Middle-of-Line in a 14 nm Node FinFET Device

This paper presents the first design reconstruction on the Front-End-of-Line and Middle-of-Line layers of a 14 nm node FinFET design. To accomplish this, a large region of interest within a custom designed 14 nm node ASIC device was delayered, imaged, and analyzed to reconstruct the GDSII design file and verify a 100% match to the golden GDSII design. This work leveraged previous developments in each stage of the front half of the cooperative Verification and Validation (V&V) workflow combined with new techniques and processes developed for processing 3D architecture FET devices. We have demonstrated the critical first step to performing a full V&V workflow on an advanced technology node device, starting from the fabricated silicon device to the design extraction. The process development knowledge gained while reaching this milestone will further accelerate future advancements toward providing trusted advanced technology node devices in a timely manner. <br>

Preparation, Imaging, and Design Extraction of the Front-End-of-Line and Middle-of-Line in a 14 nm Node FinFET Device

This paper presents the first design reconstruction on the Front-End-of-Line and Middle-of-Line layers of a 14 nm node FinFET design. To accomplish this, a large region of interest within a custom designed 14 nm node ASIC device was delayered, imaged, and analyzed to reconstruct the GDSII design file and verify a 100% match to the golden GDSII design. This work leveraged previous developments in each stage of the front half of the cooperative Verification and Validation (V&V) workflow combined with new techniques and processes developed for processing 3D architecture FET devices. We have demonstrated the critical first step to performing a full V&V workflow on an advanced technology node device, starting from the fabricated silicon device to the design extraction. The process development knowledge gained while reaching this milestone will further accelerate future advancements toward providing trusted advanced technology node devices in a timely manner. <br>

Indium Gallium Zinc Oxide FinFET Compared with Silicon FinFET

Indium gallium zinc oxide fin-field effect transistor (IGZO FinFET) characteristics are investigated and then compared with Zinc oxide fin-field effect transistor (ZnO FinFET) and the Silicon fin-field effect transistor (Si FinFET). This was done using 3D simulation. The threshold voltage for Si, ZnO, and IGZO is 0.75 V, 0.30 V and 0.05 V respectively. The silicon device has the highest transconductance (5.0 x 10-7 S) and performs better than the other devices because it has less fixed charge defects. IGZO has the second-best value of Gm (3.6 x 10-7 S), ZnO has the least value of Gm (3.4 x 10-7 S). Si device has the least drain current (IDS) value of 2.0 x 10-7 A, ZnO device has a better IDS value of 6.2 x 10-6 A while IGZO device has the best IDS value of 1.6 x 10-5 A. IGZO is better than Si by two (2) order magnitude. The field effect mobility is 50.0 cm2/Vs for all three devices.

Study Effects of Illumination and Temperature on Performance of (pn-Si) Device using Simulation Program SCAPS-1D

The current research included obtaining the best performance specifications for a silicon device with a mono-crystalline type pn junction (pn–Si). A simulation of the device was performed by the use of a computer program in one dimension SCAPS-1D in order to reach the optimum thickness for both p and n layers and to obtain the best efficiency in performance of the pn-Si junction. The optimum device efficiency was eta (η) = 12.4236 % when the ideal thickness for the p and n layers was 5µm and 1.175µm, respectively (p=5 µm and n=1.75µm). The research included studying the effects of different spectra of solar illumination using simulation of the device; the usual solar spectrum AM1_5 G1 sun. Spectrum, Black body spectrum, White spectrum constant photon flux, White spectrum constant photon power, Monochromatic spectrum constant flux, and Monochromatic spectrum constant power. The highest efficiency was obtained from the monochrome spectrum with constant power (eta (η) =22.4338 %). The effects of different temperatures on the device was studied on 250K, 300K, 350K, 400K, and 450K. The highest efficiency was revealed for Monochromatic spectrum constant power (eta (η) =24.5381 %) when the temperature was 250K.

Improve the Performance of SONOS Type UV TD Sensors Using IOHAOS with Enhanced UV Transparency ITO Gate

This research demonstrates that an indium tin oxide–silicon oxide–hafnium aluminum oxide‒silicon oxide–silicon device with enhanced UV transparency ITO gate (hereafter E-IOHAOS) can greatly increase the sensing response performance of a SONOS type ultraviolet radiation total dose (hereafter UV TD) sensor. Post annealing process is used to optimize UV optical transmission and electrical resistivity characterization in ITO film. Via nano-columns (NCols) crystalline transformation of ITO film, UV transparency of ITO film can be enhanced. UV radiation causes the threshold voltage VT of the E-IOHAOS device to increase, and the increase of the VT of E-IOHAOS device is also related to the UV TD. The experimental results show that under UV TD irradiation of 100 mW·s/cm2, ultraviolet light can change the threshold voltage VT of E-IOHAOS to 12.5 V. Moreover, the VT fading rate of ten-years retention on E-IOHAOS is below 10%. The VT change of E-IOHAOS is almost 1.25 times that of poly silicon–aluminum oxide–hafnium aluminum oxide–silicon oxide–silicon with poly silicon gate device (hereafter SAHAOS). The sensing response performance of an E-IOHAOS UV TD sensor is greatly improved by annealed ITO gate.

Thin-film synthesis of superconductor-on-insulator A15 vanadium silicide

We present a new method for thin-film synthesis of the superconducting A15 phase of vanadium silicide with critical temperature higher than 13 K. Interdiffusion between a metallic vanadium film and the underlying silicon device layer in a silicon-on-insulator substrate, at temperatures between 650 and 750 °C, favors formation of the vanadium-rich A15 phase by limiting the supply of available silicon for the reaction. Energy dispersive X-ray spectroscopy, X-ray photoelectron spectroscopy, and X-ray diffraction verify the stoichiometry and structure of the synthesized thin films. We measure superconducting critical currents of more than 106 amperes per square centimeter at low temperature in micron-scale bars fabricated from the material, and an upper critical magnetic field of 20 T, from which we deduce a superconducting coherence length of 4 nm, consistent with previously reported bulk values. The relatively high critical temperature of A15 vanadium silicide is an appealing property for use in silicon-compatible quantum devices and circuits.

Conditional quantum operation of two exchange-coupled single-donor spin qubits in a MOS-compatible silicon device

Silicon nanoelectronic devices can host single-qubit quantum logic operations with fidelity better than 99.9%. For the spins of an electron bound to a single-donor atom, introduced in the silicon by ion implantation, the quantum information can be stored for nearly 1 second. However, manufacturing a scalable quantum processor with this method is considered challenging, because of the exponential sensitivity of the exchange interaction that mediates the coupling between the qubits. Here we demonstrate the conditional, coherent control of an electron spin qubit in an exchange-coupled pair of 31P donors implanted in silicon. The coupling strength, J = 32.06 ± 0.06 MHz, is measured spectroscopically with high precision. Since the coupling is weaker than the electron-nuclear hyperfine coupling A ≈ 90 MHz which detunes the two electrons, a native two-qubit controlled-rotation gate can be obtained via a simple electron spin resonance pulse. This scheme is insensitive to the precise value of J, which makes it suitable for the scale-up of donor-based quantum computers in silicon that exploit the metal-oxide-semiconductor fabrication protocols commonly used in the classical electronics industry.