Error Performance of Subsampling Digital Power Estimation for Integrated Receivers

Estimation of signal power levels at the output of integrated receiver building blocks is a vital function as the block voltage or power gains are set based on sensed power levels to maintain constant levels at block outputs in the receiver chain. RF and IF level real-time gain settings are determined with Automatic Gain Control (AGC) loops. AGC loop circuit topologies are usually based on analog detection circuits. These analog power detection circuits are based on techniques such as envelope detection, and logarithmic amplification usually accompanied by severe accuracy issues such as Process, Voltage and Temperature (PVT) spreads preventing correct gain adjustments. Adopting a dominantly digital approach to detect the signal power would ensure a significant reduction in PVT spreads. This work presents a review of the subsampling digital power estimation to create low power digital power estimations alternative to analog methods. The simulations of the method are applied to an AM and a 64-QAM signal. Simulation results show that the power estimation error is within the acceptable level of [Formula: see text][Formula: see text]dB.

An ultra flat phased array Ku-band antenna with integrated receivers in SiGe BiCMOS

A highly integrated Ku-band (10.7–12.75 GHz) planar phased array receiver of 64 antenna elements is presented. It features instantaneous reception of the full Ku-band (2.05 GHz wide) in two orthogonal polarizations with wide scan angles by using time delay instead of phase shift. The receiver is part of a system for satellite broadcast TV reception on board of moving vehicles. Two SiGe radio frequency integrated circuits (RFICs) were developed, packaged in ceramic BGAs and assembled onto a 15-layer printed circuit board (PCB) which integrates the antenna elements. An outline of the system is given along with a detailed description. It sets a new standard in integration density. The receiver has extensive analog signal processing at intermediate frequency (IF)-level. A novel bipolar implementation for true time delay is proposed, with a continuous programmable delay range of 0…80 ps with less than 2.5 ps group-delay variation in 2 GHz bandwidth (BW). The wide BW calls for a constant group-delay implementation in the IF chain. The receiver (RFIC) consumes only 132 mW per channel. Each channel has 40 dB gain.