An Efficient VLSI Architecture Design of Antilogarithm Converter with 10-Regions Error Correction Scheme

An applications of signal processing are frequently used everywhere in day-to-day life. “Digital Signal Processing (DSP)” has been basic requirement of efficient and accurate arithmetic operations for performing fast and accurate signal processing. Logarithm arithmetic provides an option of that desire. In this work, it is presented an efficient VLSI implementation of an antilogarithm converter by using 10-region error correction. It provides error efficient implementation with significant hardware gain. VLSI implementation of reported and proposed antilogarithmic converters design created in Xilinx ISE 12.1. Antilogarithmic converters (reported and proposed design) are synthesized by using Synopsys design software perform the RTL Synthesis analysis by using package design compiler. This paper presents 10- region converter which considers design trade-off where proposed demonstrates 19.75%, 31.02%, 12.65%, 44.65% and 29.91% respective reduction in comparison of previous design. Error analysis was done using MATLAB for proposed conversion method and reported methods. Suggested antilogarithmic converters have 1.559% error only in comparison of 1.7327% error reported by Kuo et al. On behalf of hardware complexity and error analysis results, it can say that the proposed converters could perform better in comparisons of all aspects of reported design.

Design and Verification of High Performance Standard Cells for Clock Network Applications

Standard cell libraries are required by all CAD tools for chip planning. Standard cell libraries contain primitive cells required for advanced configuration. Be that as it may, more crucial cells that have been infrequently upgraded can likewise be incorporated. The principle reason for the CAD tools is to actualize the alleged RTL- to-GDS stream. Design and verification of standard cells (clock path) the advanced clock buffers and inverters present superior performance compared to the existed clock buffers and inverters. The RTL synthesis report shows that timing slack, numbers of inverters and power consumption have been reduced by 65.9%, 80.5% and 5.1% respectively.

Design and Implementation of Radar Cross-Section Models on a Virtex-6 FPGA

The simulation of radar cross-section (RCS) models in FPGA is illustrated. The models adopted are the Swerling ones. Radar cross-section (RCS) which is also termed as echo area gives the amount of scattered power from a target towards the radar. This paper elucidates the simulation of RCS to represent the specified targets under different conditions, namely, aspect angle and frequency. This model is used for the performance evaluation of radar. RCS models have been developed for various targets like simple objects to complex objects like aircrafts, missiles, tanks, and so forth. First, the model was developed in MATLAB real time simulation environment and after successful verification, the same was implemented in FPGA. Xilinx ISE software was used for VHDL coding. This simulation model was used for the testing of a radar system. The results were compared with MATLAB simulations and FPGA based timing diagrams and RTL synthesis. The paper illustrates the simulation of various target radar cross-section (RCS) models. These models are simulated in MATLAB and in FPGA, with the aim of implementing them efficiently on a radar system. This method can be generalized to apply to objects of arbitrary geometry for the two configurations of transmitter and receiver in the same as well as different locations.