Design and Verification of High Performance Standard Cells for Clock Network Applications

2018 ◽  
Vol 24 (8) ◽  
pp. 5877-5883 ◽  
Author(s):  
S Ravi ◽  
Suprovab Mandal ◽  
Harish M Kittur
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Superior Performance ◽  
Performance Standard ◽  
Standard Cell ◽  
Cad Tools ◽  
Network Applications ◽  
Standard Cells ◽  
Rtl Synthesis ◽  
Synthesis Report

Standard cell libraries are required by all CAD tools for chip planning. Standard cell libraries contain primitive cells required for advanced configuration. Be that as it may, more crucial cells that have been infrequently upgraded can likewise be incorporated. The principle reason for the CAD tools is to actualize the alleged RTL- to-GDS stream. Design and verification of standard cells (clock path) the advanced clock buffers and inverters present superior performance compared to the existed clock buffers and inverters. The RTL synthesis report shows that timing slack, numbers of inverters and power consumption have been reduced by 65.9%, 80.5% and 5.1% respectively.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 55-62
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Clock Frequency ◽  
Charge Sharing ◽  
Benchmark Circuit ◽  
Domino Circuit ◽  
Power Delay Product ◽  
Domino Circuits ◽  
Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

Low ECD High Performance Invert Emulsion Drilling Fluids: Lab Development and Field Deployment

2021 ◽  
Author(s):  
Vikrant Wagle ◽  
Abdullah Yami ◽  
Michael Onoriode ◽  
Jacques Butcher ◽  
Nivika Gupta
Keyword(s):  
High Performance ◽  
Filter Cake ◽  
Drilling Fluid ◽  
Field Performance ◽  
Superior Performance ◽  
Core Material ◽  
Drilling Fluids ◽  
Invert Emulsion ◽  
Field Deployment ◽  
Permeability Studies

Abstract The present paper describes the results of the formulation of an acid-soluble low ECD organoclay-free invert emulsion drilling fluid formulated with acid soluble manganese tetroxide and a specially designed bridging package. The paper also presents a short summary of field applications to date. The novel, non-damaging fluid has superior rheology resulting in lower ECD, excellent suspension properties for effective hole cleaning and barite-sag resistance while also reducing the risk of stuck pipe in high over balance applications. 95pcf high performance invert emulsion fluid (HPIEF) was formulated using an engineered bridging package comprising of acid-soluble bridging agents and an acid-soluble weighting agent viz. manganese tetroxide. The paper describes the filtration and rheological properties of the HPIEF after hot rolling at 300oF. Different tests such as contamination testing, sag-factor analysis, high temperature-high pressure rheology measurements and filter-cake breaking studies at 300oF were performed on the HPIEF. The 95pcf fluid was also subjected to particle plugging experiments to determine the invasion characteristics and the non-damaging nature of the fluids. The 95pcf HPIEF exhibited optimal filtration properties at high overbalance conditions. The low PV values and rheological profile support low ECDs while drilling. The static aging tests performed on the 95pcf HPIEF resulted in a sag factor of less than 0.53, qualifying the inherent stability for expected downhole conditions. The HPIEF demonstrated resilience to contamination testing with negligible change in properties. Filter-cake breaking experiments performed using a specially designed breaker fluid system gave high filter-cake breaking efficiency. Return permeability studies were performed with the HPIEF against synthetic core material, results of which confirmed the non-damaging design of the fluid. The paper thus demonstrates the superior performance of the HPIEF in achieving the desired lab and field performance.

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