Маска на основе эпитаксиального слоя Si для самокаталитического роста нитевидных нанокристаллов на подложках GaAs (111)B и (100)

GaAs nanowire (NW) self-catalyzed growth on GaAs (111) B and GaAs (100) substrates was carried out by molecular beam epitaxy. A mask for the self-catalyzed NW growth was created by oxidizing an epitaxial silicon layer grown on the GaAs surface by molecular beam epitaxy (MBE). Silicon oxidation was realized in an atmosphere of purified air under normal conditions without moving the structures out from the vacuum system volume of the molecular beam epitaxy chamber. The oxidation process of a silicon layer was studied using single-wave and spectral ellipsometry and the surface morphology of oxidized silicon was studied by atomic force microscopy. Substrates with NWs were studied by scanning electron microscopy. The NW density was demonstrated to be 2.6•107 cm-2 and 3•107 cm-2 for (111)B and (100), respectively.

Влияние твердофазной рекристаллизации с двойной имплантацией на плотность структурных дефектов в ультратонких слоях кремния на сапфире

The main technological problem in the manufacture of electronics on silicon-on-sapphire (SOS) wafers is the high density of defects in the epitaxial silicon layer. The modern method of obtaining ultrathin SOS wafers using solid-phase epitaxial recrystallization (SPER) and pyrogenic thinning that significantly reduce the defect density in these layers. Nevertheless, the influence of the defect density in submicron SOS layers on the structural quality of ultrathin SOS layers remains unclear. In this work, ultrathin (100 nm) SOS wafers were obtained by SPER of submicron (300 nm) SOS wafers with different structural quality. The crystallinity of 300 nm layers before the recrystallization process and ultrathin layers was determined by XRD and TEM. It was found that the smallest values of the FWHM 0.19-0.20° were observed for the ultrathin SOS layers obtained on the basis of 300 nm SOS wafers with the best structural quality. It was shown that the structural perfect near-surface Si layer, which serves as a seed layer in SPER process, and the double implantation regime allow to reduce the linear defect density in the ultrathin SOS layers by ~ 1×104 cm-1.

CONTROLLED PROCESSES OF THE PARAMETERS TRANSFORMATION BY ION BEAMS IN SILICON BIPOLAR MICROWAVE TRANSISTORS

The paper considers the formation of a transition layer of Mo - Si contacts, as well as the effect of Mo film deposition regimes and methods of heat treatment of contacts. It was found that when forming contacts of microwave transistors, by deposition of a Mo film on the surface of an epitaxial silicon layer, the structure of the latter depends on the dose of doping with phosphorus ions and on the temperature of post-implantation annealing. The results of experiments and two-dimensional physico-mathematical modeling to study the dependence of the parameters of test samples of the KT916A transistor depending on the dose of matching the emitters with phosphorus ions through a molybdenum film are presented. It is shown that with an increase in the doping dose, the surface and maximum concentration of phosphorus increases. At the same time, both energy and frequency characteristics of the transistor are improved, and the radiation resistance increases.

A Technique for Source/Drain Elevation using Implantation Mediated Selective Etching

A process involving implantation mediated selective etching has been developed for Source/Drain elevation of CMOS devices. 100 nm thick epitaxial silicon/polysilicon layer was formed on patterned Si/SiO2 structure by chemical vapor deposition (CVD) at 700°C. Structural damage was selectively introduced in polysilicon layer by a low dose Argon implantation at 140 keV. Crystal damage in epitaxial silicon layer was kept minimum by aligning the implantation in vertical <100> channeling direction. A short duration post-anneal at 420°C was usedfor structural recovery of the silicon layer. Polysilicon layer was then removed by wet etching with more than an order of magnitude selectivity over epitaxial silicon. The resulting structure of elevated silicon is free from faceting effects. The process is independent of sidewall/isolation materials, and not bound by thickness limits.

Strained Ge Channel p-type MOSFETs Fabricated on Si1−xGex/Si Virtual Substrates

We have fabricated strained Ge channel p-type metal oxide semiconductor field-effect transistors (p-MOSFETs) on Si1−xGex (x=0.7 to 0.9) virtual substrates. Capping the channel with a relaxed, epitaxial silicon layer eliminates the poor interface between silicon dioxide (SiO2) and pure Ge. The effects of the Si cap thickness, the strain in the Ge channel, and the thickness of the Ge channel on hole mobility enhancement were investigated. Optimized strained Ge p-MOSFETs show hole mobility enhancements of nearly 8 times that of co-processed bulk Si devices across a wide range of vertical field. These devices demonstrate that the high mobility holes in strained Ge can be utilized in a MOS device despite the need to cap the channel with a highly dislocated Si layer.