Modeling of Threshold Voltage Hysteresis in SiC MOSFET Device

2020 ◽  
Vol 1004 ◽  
pp. 671-679 ◽  
Author(s):  
Salvatore Cascino ◽  
Mario Saggio ◽  
Alfio Guarnera
Keyword(s):  
Threshold Voltage ◽  
Instability Threshold ◽  
Positive Threshold ◽  
Voltage Hysteresis ◽  
Simulation Results ◽  
Oxide Traps ◽  
Limited Depth ◽  
Stress Voltage

In this paper, we report on the simulation results of instability threshold voltage of SiC MOSFET device. Hysteresis cycles of threshold voltage suggest that trapping and detrapping phenomena of electrons from the SiC layer into the oxide traps occur. Experiment suggests that positive threshold voltage shifts (ΔVth) caused by a positive stress voltage to the gate, are almost fully recovered by applying negative stress voltage. This work assumes uniform trap densities extending from SiC interface at a limited depth into oxide.

Effect of Temperature and Al Concentration on the Electrical Performance of GaN and Al0.2Ga0.8N Accumulation-Mode FET Devices

2010 ◽  
Vol 645-648 ◽  
pp. 1215-1218
Author(s):  
Marko J. Tadjer ◽  
Karl D. Hobart ◽  
Michael A. Mastro ◽  
Travis J. Anderson ◽  
Eugene A. Imhoff ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Field Effect Transistors ◽  
Chemical Vapor ◽  
Drain Current ◽  
Electrical Performance ◽  
Effect Of Temperature ◽  
Organic Chemical ◽  
N Accumulation ◽  
Positive Threshold ◽  
Aln Buffer

Field-effect transistors were fabricated on GaN and Al0.2Ga0.8N epitaxial layers grown by metal organic chemical vapor deposition (MOCVD) on sapphire substrates. The threshold voltage VTH was higher when AlGaN was used as an active layer. VTH also increased with temperature due to the increased positive polarization charge at the GaN/AlN buffer/sapphire interfaces. Drain current increased at high temperatures even with more positive threshold voltage, which makes GaN-based FET devices attractive for high temperature operation.

Performance of ZnO TFTs with AlN as Insulator

2007 ◽  
Vol 1035 ◽  
Author(s):  
Maria Merlyne De Souza ◽  
Richard B Cross ◽  
Suhas Jejurikar ◽  
K P Adhi
Keyword(s):  
Surface Roughness ◽  
Threshold Voltage ◽  
Rf Sputtering ◽  
Interface States ◽  
Aluminium Nitride ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Positive Threshold ◽  
The Stability

AbstractThe performance of ZnO TFTs fabricated via RF sputtering, with Aluminium Nitride (AlN) as the underlying insulator are reported. The surface roughness of ZnO with AlN is lower than that with SiN by at least 5 times, and that with SiO2 by 30 times. The resulting mobility for the three insulators AlN, SiN, SiO2 using identical process is found to be 3, 0.2-0.7 and 0.1-0.25 cm2/Vs respectively. There does not appear to be any corresponding improvement in the stability of the AlN devices. The devices demonstrate significant positive threshold voltage shift with positive gate bias and negative threshold voltage shift with negative gate bias. The underlying cause is surmised to be ultra-fast interface states in combination with bulk traps in the ZnO.

Threshold-Voltage Instability in SiC MOSFETs Due to Near-Interfacial Oxide Traps

2016 ◽  
Vol 858 ◽  
pp. 585-590 ◽  
Author(s):  
Aivars J. Lelis ◽  
Ronald Green ◽  
Daniel B. Habersat
Keyword(s):  
Threshold Voltage ◽  
Charge Trapping ◽  
Test Methods ◽  
Device Failure ◽  
Voltage Instability ◽  
Oxide Trap ◽  
Oxide Traps ◽  
Trap Activation

There are two basic mechanisms that affect the threshold-voltage (VT) stability: oxide-trap activation and oxide-trap charging. Once additional oxide traps are activated, then they are free to participate in the charge-trapping processes that can, especially for older vintage devices, result in large VT shifts and potential device failure. More recent commercially-available devices show much smaller effects, and minimal trap activation. Given the dramatic improvements, it is now imperative that improved test methods be employed to properly separate out bad devices from good devices.

The Research on Static Characteristics of 1700V/100A Planner NPT-IGBT

2013 ◽  
Vol 433-435 ◽  
pp. 1572-1577
Author(s):  
Ming Chao Gao ◽  
Jun Liu ◽  
Ge Zhao ◽  
Jiang Liu ◽  
Rui Jin ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Threshold Voltage ◽  
Process Simulation ◽  
Cell Structure ◽  
Test Results ◽  
Static Characteristics ◽  
Injection Dose ◽  
Simulation Results

A 1700V/100A NPT-IGBT was designed by process simulation, which had an internal transparent collector and a planner cell structure. The Static characteristics were studied. The simulation results show that the threshold voltage of the device can be adjusted by changing the injection dose or the drive-in time of the p-well. The saturation voltage of the device can be adjusted by changing injection dose of the p-well or the internal transparent collector. This device was fabricated using a self-aligned process, the test results show that the breakdown voltage is more than 2100V, the saturation voltage is between 2.5V and 2.7V and the threshold voltage is between 3.9V and 5.9V, which are similar with the simulation results.

Positive Threshold-Voltage Shift of Y2O3Gate Dielectric InAlN/GaN-on-Si (111) MOSHEMTs with Respect to HEMTs

2014 ◽  
Vol 3 (6) ◽  
pp. Q120-Q126 ◽  
Author(s):  
M. K. Bera ◽  
Y. Liu ◽  
L. M. Kyaw ◽  
Y. J. Ngoo ◽  
S. P. Singh ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Positive Threshold ◽  
Gan On Si

A Threshold Voltage Simulation of Hydrogen-Terminated Diamond MESFETs

2012 ◽  
Vol 482-484 ◽  
pp. 1093-1096 ◽  
Author(s):  
Xiao Feng Zhuang ◽  
Qing Kai Zeng ◽  
Bing Ren ◽  
Zhen Hua Wang ◽  
Yue Lu Zhang ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Diamond Film ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Diamond Surface ◽  
Gate Length ◽  
Simulation Results ◽  
Surface Conduction ◽  
Conduction Layer

In this paper, the threshold voltage of diamond film-based metal-semiconductor field effect transistors (MESFETs) has been simulated using Silvaco TCAD tools. The drain current (Id) versus gate voltage (Vg) relationship, and the distribution of acceptors in diamond surface conduction layer were also investigated. From the simulation results, it was found that the gate length contributed the most to the threshold voltage, while the doping depth almost had no impact on the threshold voltage value.

Bias Stress-Induced Threshold-Voltage Instability of SiC MOSFETs

2006 ◽  
Vol 527-529 ◽  
pp. 1317-1320 ◽  
Author(s):  
Aivars J. Lelis ◽  
Daniel B. Habersat ◽  
G. Lopez ◽  
J.M. McGarrity ◽  
F. Barry McLean ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Linear Increase ◽  
Oxide Semiconductor ◽  
Bias Stress ◽  
Voltage Instability ◽  
Current Voltage ◽  
Oxide Traps ◽  
Charge Tunneling

We have observed instability in the threshold voltage, VT, of SiC metal-oxide semiconductor field-effect transistors (MOSFETs) due to gate-bias stressing. This effect has routinely been observed by us in all 4H and 6H SiC MOSFETs from three different manufacturers—even at room temperature. A positive-bias stress, applying an electric field of about 1 to 2 MV/cm across the gate oxide, for 3 minutes followed by a negative-bias stress for another 3 minutes typically results in a shift of the ID-VGS current-voltage characteristic in the range of 0.25 to 0.5 V and is repeatable. We speculate that this effect is due to the presence of a large number of near-interfacial oxide traps that presumably lie in the oxide transition region that extends several nm into the oxide from the SiC interface, caused by the presence of C and strained SiO2. This instability is consistent with charge tunneling in and out of these near-interfacial oxide traps, which in irradiated Si MOSFETs has been attributed to border traps. Also consistent with charge tunneling is the observed linear increase in the magnitude of the SiC VT instability with log (time).

scholarly journals Gamma-ray irradiation and post-irradiation at room and elevated temperature response of pMOS dosimeters with thick gate oxides

2011 ◽  
Vol 26 (3) ◽  
pp. 261-265 ◽  
Author(s):  
Momcilo Pejovic ◽  
Svetlana Pejovic ◽  
Edin Dolicanin ◽  
Djordje Lazarevic
Keyword(s):  
Elevated Temperature ◽  
Threshold Voltage ◽  
Gamma Ray ◽  
Temperature Response ◽  
Oxide Thickness ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Post Irradiation ◽  
Gamma Ray Irradiation ◽  
Oxide Traps

Gamma-ray irradiation and post-irradiation response at room and elevated temperature have been studied for radiation sensitive pMOS transistors with gate oxide thickness of 100 and 400 nm, respectively. Their response was followed based on the changes in the threshold voltage shift which was estimated on the basis of transfer characteristics in saturation. The presence of radiation-induced fixed oxide traps and switching traps - which lead to a change in the threshold voltage - was estimated from the sub-threshold I-V curves, using the midgap technique. It was shown that fixed oxide traps have a dominant influence on the change in the threshold voltage shift during gamma-ray irradiation and annealing.

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