Characterization of Wire-Bonding on LDS Materials and HF-PCBs for High-Frequency Applications

Thermosonic wire bonding is a well-established process. However, when working on advanced substrate materials and the associated required metallization processes to realize innovative applications, multiple factors impede the straightforward utilization of the known process. Most prominently, the surface roughness was investigated regarding bond quality in the past. The practical application of wire bonding on difficult-to-bond substrates showed inhomogeneous results regarding this quality characteristic. This study describes investigations on the correlation among the surface roughness, profile peak density and bonding quality of Au wire bonds on thermoplastic and thermoset-based substrates used for high-frequency (HF) applications and other high-end applications. FR4 PCB (printed circuit board flame resitant class 4) were used as references and compared to HF-PCBs based on thermoset substrates with glass fabric and ceramic filler as well as technical thermoplastic materials qualified for laser direct structuring (LDS), namely LCP (liquid crystal polymer), PEEK (polyether ether ketone) and PTFE (polytetrafluoroethylene). These LDS materials for HF applications were metallized using autocatalytic metal deposition to enable three-dimensional structuring, eventually. For that purpose, bond parameters were investigated on the mentioned test substrates and compared with state-of-the-art wire bonding on FR4 substrates as used for HF applications. Due to the challenges of the limited thermal conductivity and softening of such materials under thermal load, the surface temperatures were matched up by thermography and the adaptation of thermal input. Pull tests were carried out to determine the bond quality with regard to surface roughness. Furthermore, strategies to increase reliability by the stitch-on-ball method were successfully applied.

Parametric Optimization of Integrated Circuit Assembly Process: An Evolutionary Computing-Based Approach

Strict demands for very tight tolerances and increasing complexity in the semiconductors’ assembly impose a need for an accurate parametric design that deals with multiple conflicting requirements. This paper presents application of the advanced optimization methodology, based on evolutionary algorithms (EAs), on two studies addressing parametric optimization of the wire bonding process in the semiconductors’ assembly. The methodology involves statistical pre-processing of the experimental data, followed by an accurate process modeling by artificial neural networks (ANNs). Using the neural model, the process parameters are optimized by four metaheuristics: the two most commonly used algorithms – genetic algorithm (GA) and simulated annealing (SA), and the two newly designed algorithms that have been rarely utilized in semiconductor assembly optimizations – teaching-learning based optimization (TLBO) and Jaya algorithm. The four algorithm performances in two wire bonding studies are benchmarked, considering the accuracy of the obtained solutions and the convergence rate. In addition, influence of the algorithm hyper-parameters on the algorithms effectiveness is rigorously discussed, and the directions for the algorithm selection and settings are suggested. The results from two studies clearly indicate superiority of the TLBO and Jaya algorithms over GA and SA, especially in terms of the solution accuracy and the built-in algorithm robustness. Furthermore, the proposed evolutionary computing-based optimization methodology significantly outperforms the four frequently used methods from the literature, explicitly demonstrating effectiveness and accuracy in locating global optimum for delicate optimization problems.

Improvement of inter layer dielectric crack for LQFP C90FG wafer technology devices in copper wire bonding process

Purpose This paper aims to investigate the root causes of and implement the improvements for the inter layer dielectric (ILD) crack for LQFP C90FG (CMOS90 Floating Gate) wafer technology devices in copper wire bonding process. Design/methodology/approach Failure analysis was conducted including cratering, scanning electron microscopy inspection and focus ion beam cross-section analysis, which showed ILD crack. Root cause investigation of ILD crack rate sudden jumping was carried out with cause-and-effect analysis, which revealed the root cause is shallower lead frame down-set. ILD crack mechanism deep-dive on ILD crack due to shallower lead frame down-set, which revealed the mechanism is lead frame flag floating on heat insert. Further investigation and energy dispersive X-ray analysis found the Cu particles on heat insert is another factor that can result in lead frame flag floating. Findings Lead frame flag floating on heat insert caused by shallower lead frame down-set or foreign matter on heat insert is a critical factor of ILD crack that has never been revealed before. Weak wafer structure strength caused by thinner wafer passivation1 thickness and sharp corner at Metal Trench (compared with the benchmarking fab) are other factors that can impact ILD crack. Originality/value For ILD crack improvement in copper wire bonding, besides the obvious factors such as wafer structure and wire bonding parameters, also should take other factors into consideration including lead frame flag floating on heat insert and heat insert maintenance.