scholarly journals Characterization of Wire-Bonding on LDS Materials and HF-PCBs for High-Frequency Applications

2022 ◽  
Vol 6 (1) ◽  
pp. 9
Author(s):  
Thomas Guenther ◽  
Kai Werum ◽  
Ernst Müller ◽  
Marius Wolf ◽  
André Zimmermann
Keyword(s):  
Surface Roughness ◽  
High Frequency ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Wire Bonding ◽  
Circuit Board ◽  
Quality Characteristic ◽  
Bond Quality ◽  
Wire Bonds ◽  
Pull Tests

Thermosonic wire bonding is a well-established process. However, when working on advanced substrate materials and the associated required metallization processes to realize innovative applications, multiple factors impede the straightforward utilization of the known process. Most prominently, the surface roughness was investigated regarding bond quality in the past. The practical application of wire bonding on difficult-to-bond substrates showed inhomogeneous results regarding this quality characteristic. This study describes investigations on the correlation among the surface roughness, profile peak density and bonding quality of Au wire bonds on thermoplastic and thermoset-based substrates used for high-frequency (HF) applications and other high-end applications. FR4 PCB (printed circuit board flame resitant class 4) were used as references and compared to HF-PCBs based on thermoset substrates with glass fabric and ceramic filler as well as technical thermoplastic materials qualified for laser direct structuring (LDS), namely LCP (liquid crystal polymer), PEEK (polyether ether ketone) and PTFE (polytetrafluoroethylene). These LDS materials for HF applications were metallized using autocatalytic metal deposition to enable three-dimensional structuring, eventually. For that purpose, bond parameters were investigated on the mentioned test substrates and compared with state-of-the-art wire bonding on FR4 substrates as used for HF applications. Due to the challenges of the limited thermal conductivity and softening of such materials under thermal load, the surface temperatures were matched up by thermography and the adaptation of thermal input. Pull tests were carried out to determine the bond quality with regard to surface roughness. Furthermore, strategies to increase reliability by the stitch-on-ball method were successfully applied.

Electrical Characterization of Low-Profile Copper Foil for Reduced Surface Roughness Loss

2016 ◽  
Vol 2016 (1) ◽  
pp. 000358-000363 ◽  
Author(s):  
Qianfei Su ◽  
A. Ege Engin ◽  
Jerry Aguirre
Keyword(s):  
Surface Roughness ◽  
Cross Sections ◽  
Transmission Lines ◽  
High Frequency ◽  
Printed Circuit Board ◽  
Electrical Characterization ◽  
Cavity Resonator ◽  
Circuit Board ◽  
Low Profile ◽  
Measure Surface Roughness

Abstract Signal attenuation in transmission lines is a major issue for reliable transmission in high frequency range. Knowledge of the electrical parameters of printed circuit board (PCB), including dielectric constant and loss tangent, is critical. Moreover, surface roughness has a great effect on loss in high frequency. This paper demonstrates an effective simulation fitting method for electrical material characterization. Cavity resonator is chosen as the circuit for characterization. A methodology is presented to measure surface roughness from cross sections, and compared with values extracted from resonator measurements. Several materials and copper foils treatments, including low-profile, are analyzed in this paper.

Failure analysis on electrolytic Ni/Au surface finish of PCB used for wire bonding and soldering

2014 ◽  
Vol 26 (4) ◽  
pp. 180-193 ◽  
Author(s):  
Fei-Jun Chen ◽  
Shi Yan ◽  
Zhen-Guo Yang
Keyword(s):  
Surface Finish ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Wire Bonding ◽  
Circuit Board ◽  
Great Loss ◽  
Content Type ◽  
Stereo Microscope ◽  
Gold Wires ◽  
Micro Morphology

Purpose – The purpose of this study is to address two kinds of printed circuit board (PCB) failures with electrolytic Ni/Au as the surface finish. One was the weak bondability of gold wires to Ni/Au pads and the other was “dull gold” and weak solder wettability, which both caused great loss for the PCB manufacturer. Design/methodology/approach – The failure samples were studied and analyzed in terms of macro- and micro-morphology of the surface finish, its element composition and thickness by various characterization techniques, such as three-dimensional stereo microscope, scanning electron microscope, energy dispersive spectroscopy and X-ray fluorescence spectrum. Findings – Then the causes of the two failures were both found to be the inadequate thickness of gold deposit and other surface finish defects, but these causes played different roles in either failure or the mechanisms differ. Finally, their failure mechanisms were discussed and corresponding countermeasures were put forward for prevention. Practical implications – This study not only addresses a practical failure problem but also provides some clues to a better and further understanding of the effect of PCB process and management on its quality and reliability in manufacturing practice. Originality/value – It sheds light on how the thickness and quality of surface finish affects its wire bonding and soldering performances.

scholarly journals Parasitic Loop Inductances Reduction in the PCB Layout in GaN-Based Power Converters Using S-Parameters and EM Simulations

Energies ◽  
2021 ◽  
Vol 14 (5) ◽  
pp. 1495
Author(s):  
Loris Pace ◽  
Nadir Idir ◽  
Thierry Duquesne ◽  
Jean-Claude De Jaeger
Keyword(s):  
High Frequency ◽  
Printed Circuit Board ◽  
Power Converters ◽  
Calibration Procedure ◽  
Circuit Board ◽  
Design System ◽  
Switching Speed ◽  
Parasitic Inductance ◽  
Frequency Converters ◽  
S Parameters

Due to the high switching speed of Gallium Nitride (GaN) transistors, parasitic inductances have significant impacts on power losses and electromagnetic interferences (EMI) in GaN-based power converters. Thus, the proper design of high-frequency converters in a simulation tool requires accurate electromagnetic (EM) modeling of the commutation loops. This work proposes an EM modeling of the parasitic inductance of a GaN-based commutation cell on a printed circuit board (PCB) using Advanced Design System (ADS®) software. Two different PCB designs of the commutation loop, lateral (single-sided) and vertical (double-sided) are characterized in terms of parasitic inductance contribution. An experimental approach based on S-parameters, the Cold FET technique and a specific calibration procedure is developed to obtain reference values for comparison with the proposed models. First, lateral and vertical PCB loop inductances are extracted. Then, the whole commutation loop inductances including the packaging of the GaN transistors are determined by developing an EM model of the device’s internal parasitic. The switching waveforms of the GaN transistors in a 1 MHz DC/DC converter are given for the different commutation loop designs. Finally, a discussion is proposed on the presented results and the development of advanced tools for high-frequency GaN-based power electronics design.

Three Dimensional Detection of the via in the PCB CT Image Using Morphology Operation

2015 ◽  
Vol 752-753 ◽  
pp. 1406-1412
Author(s):  
Lei Zeng ◽  
Jian Chen ◽  
Han Ning Li ◽  
Bin Yan ◽  
Yi Fu Xu ◽  
...  
Keyword(s):  
Nondestructive Testing ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Detection Algorithm ◽  
Circuit Board ◽  
Dimensional Structure ◽  
Three Dimension ◽  
Shape Information ◽  
Printed Circuit ◽  
Testing Technology

In modern industry, the nondestructive testing of printed circuit board (PCB) can prevent effectively the system failure and is becoming more and more important. As a vital part of the PCB, the via connects the devices, the components and the wires and plays a very important role for the connection of the circuits. With the development of testing technology, the nondestructive testing of the via extends from two dimension to three dimension in recent years. This paper proposes a three dimensional detection algorithm using morphology method to test the via. The proposed algorithm takes full advantage of the three dimensional structure and shape information of the via. We have used the proposed method to detect via from PCB images with different size and quality, and found the detection performances to be very encouraging.

Numerical Investigation of Heat Transfer of Twelve Plastic Leaded Chip Carrier (PLCC) by Using Computational Fluid Dynamic, FLUENTTM Software

2013 ◽  
Vol 795 ◽  
pp. 603-610 ◽  
Author(s):  
Mohamed Mazlan ◽  
A. Rahim ◽  
M.A. Iqbal ◽  
Mohd Mustafa Al Bakri Abdullah ◽  
W. Razak ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Fluid Dynamic ◽  
Three Dimensional ◽  
Circuit Board ◽  
Junction Temperature ◽  
Inlet Velocity ◽  
Chip Carrier ◽  
Flow Through ◽  
Package Density ◽  
Heat And Fluid Flow

Plastic Leaded Chip Carrier (PLCC) package has been emerged a promising option to tackle the thermal management issue of micro-electronic devices. In the present study, three dimensional numerical analysis of heat and fluid flow through PLCC packages oriented in-line and mounted horizontally on a printed circuit board, is carried out using a commercial CFD code, FLUENTTM. The simulation is performed for 12 PLCC under different inlet velocities and chip powers. The contours of average junction temperatures are obtained for each package under different conditions. It is observed that the junction temperature of the packages decreases with increase in inlet velocity and increases with chip power. Moreover, the increase in package density significantly contributed to rise in temperature of chips. Thus the present simulation demonstrates that the chip density (the number of packages mounted on a given area), chip power and the coolant inlet velocity are strongly interconnected; hence their appropriate choice would be crucial.

Integration of a K-Band Receiver Front-End Using a Copper Core Printed Circuit Board

2018 ◽  
Vol 2018 (1) ◽  
pp. 000384-000388
Author(s):  
Brian Curran ◽  
Jacob Reyes ◽  
Christian Tschoban ◽  
Ivan Ndip ◽  
Klaus-Dieter Lang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Antenna Arrays ◽  
High Frequency ◽  
Printed Circuit Board ◽  
Cost Effective ◽  
Circuit Board ◽  
Front End ◽  
High Bandwidth ◽  
Increasing Demand ◽  
K Band

Abstract Increasing demand for high bandwidth wireless satellite connections and telecommunications has resulted in interest in steerable antenna arrays in the GHz frequency range. These applications require cost-effective integration technologies for high frequency and high power integrated circuits (ICs) using GaAs, for example. In this paper, an integration platform is proposed, that enables GaAs ICs to be directly placed on a copper core inside cavities of a high frequency laminate for optimal cooling purposes. The platform is used to integrate a K-Band receiver front-end, composed of four GaAs ICs, with linear IF output power for input powers above −40dBm and a temperature of 42°C during operation.

Comparison of Different Methods for Stress and Deflection Analysis in Embedded Die Packages during the Assembly Process

2014 ◽  
Vol 2014 (1) ◽  
pp. 000355-000360
Author(s):  
K. Macurova ◽  
R. Bermejo ◽  
M. Pletz ◽  
R. Schöngrundner ◽  
T. Antretter ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Plastic Material ◽  
Three Dimensional ◽  
Diffraction Method ◽  
Element Model ◽  
Analytical Investigation ◽  
Circuit Board ◽  
Curvature Radius ◽  
Assembly Process ◽  
Deflection Analysis

Important topics for electronic packages are thermally induced stresses created during package manufacturing and their role in mechanical failure. In the present paper, an analytical and a numerical analysis of the assembly process (component attached with an adhesive to a copper foil) is investigated. This process is prior to the lamination of the printed circuit board. Stresses develop due to a mismatch of coefficients of thermal expansion and particularly to shrinkage associated with adhesive polymerization. The analytical investigation is based on the classical laminate theory and an interfacial model. The three-dimensional numerical finite element model is capable to use geometric and material properties which are not possible to investigate analytically. In particular, the influence of the adhesive meniscus and plastic material models for copper and adhesive are investigated. The models are validated experimentally by an X-ray diffraction method (Rocking-Curve-Technique) showing a good agreement of the calculated and measured curvature radius values.

Comparison of Different Methods for Stress and Deflection Analysis in Embedded Die Packages During the Assembly Process

2015 ◽  
Vol 12 (2) ◽  
pp. 80-85 ◽  
Author(s):  
K. Macurova ◽  
R. Bermejo ◽  
M. Pletz ◽  
R. Schöngrundner ◽  
T. Antretter ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Plastic Material ◽  
Three Dimensional ◽  
Diffraction Method ◽  
Element Model ◽  
Analytical Investigation ◽  
Circuit Board ◽  
Curvature Radius ◽  
Assembly Process ◽  
Deflection Analysis

Important topics for electronic packages are thermally induced stresses created during package manufacturing and their role in mechanical failure. In the present paper, an analytical and a numerical analysis of the assembly process (component attached with an adhesive to a copper foil) is investigated. This process is prior to the lamination of the printed circuit board. Stresses develop due to a mismatch of coefficients of thermal expansion and particularly to shrinkage associated with adhesive polymerization. The analytical investigation is based on the classical laminate theory and an interfacial model. The three-dimensional, numerical, finite element model is capable of using geometric and material properties not possible to investigate analytically. In particular, the influence of the adhesive meniscus and plastic material models for copper and adhesive are investigated. The models are validated experimentally by an x-ray diffraction method (rocking-curve technique) showing a good agreement of the calculated and measured curvature radius values.

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