Characteristics of MPSoC Based On Dual Feedback Edge Triggered Flip Flop

With the persistent scaling of semiconductor technology, the embedded multi-processor platforms lifetime reliability has been the primary concern for the industry. The advancements in technology permit several microprocessors integration, dedicated digital hardware, and at times mixed-signal circuits on a single silicon die, specifically multi-processor system-on-a-chip (MPSoC). In this paper, the design and analysis of CMOS based MPSoC is made. A CMOS based MPSoC is designed with 45nm technology. In this design, ADC converter is used in which 10-bit data is given as input, and are converted into digital data. A double feedback edge triggered flip flop is designed. The implementation of flip flop, based on both feedback and triggering process, is more effective in the elimination of error occurrence. Power Gating (PG) technique is proposed which exploits the stacking effect to achieve high energy efficiency. Binary controlled stacked SRAM cell, based on a parallel cross-coupling feedback controller, is implemented to reduce the leakage loss and ground bouncing noise. An inverter, based on NMOS and CMOS, is used for the inverting process. The input voltage of 5v is given and is varied. Then, a 2-bit counter is employed, which is responsible for counting down or counting up. The counter should count down if the signal is high. The counter should count up, if the signal is low. Thus, this design will be helpful in the implementation of compact processing system which may also be employed for many real-time applications where there is a need of compact device. The benefits of this multi processors integration will be helpful in speeding the process thereby reducing the leakage power loss, power consumption, delay factor and so on. The analysis of performance is carried out using CMOS based Tanner EDA, and the outcomes are represented.

Utilization of Power Gating Technique for the Analysis of MPSoC Based On Dual Feedback Edge Triggered Flip Flop

With the persistent scaling of semiconductor technology, the embedded multi-processor platforms lifetime reliability has been the primary concern for the industry. The advancements in technology permit several microprocessors integration, dedicated digital hardware, and at times mixed-signal circuits on a single silicon die, specifically multi-processor system-on-a-chip (MPSoC). In this paper, the design and analysis of CMOS based MPSoC is made. A CMOS based MPSoC is designed with 45nm technology. In this design, ADC converter is used in which 10-bit data is given as input, and are converted into digital data. A double feedback edge triggered flip flop is designed. The implementation of flip flop, based on both feedback and triggering process, is more effective in the elimination of error occurrence. Power Gating (PG) technique is proposed which exploits the stacking effect to achieve high energy efficiency. Binary controlled stacked SRAM cell, based on a parallel cross-coupling feedback controller, is implemented to reduce the leakage loss and ground bouncing noise. An inverter, based on NMOS and CMOS, is used for the inverting process. The input voltage of 5v is given and is varied. Then, a 2-bit counter is employed, which is responsible for counting down or counting up. The counter should count down if the signal is high. The counter should count up, if the signal is low. Thus, this design will be helpful in the implementation of compact processing system which may also be employed for many real-time applications where there is a need of compact device. The benefits of this multi processors integration will be helpful in speeding the process thereby reducing the leakage power loss, power consumption, delay factor and so on. The analysis of performance is carried out using CMOS based Tanner EDA, and the outcomes are represented.

NOISE-AWARE DATA PRESERVING SEQUENTIAL MTCMOS CIRCUITS WITH DYNAMIC FORWARD BODY BIAS

Multi-threshold voltage CMOS (MTCMOS) is the most widely used circuit technique for suppressing the subthreshold leakage currents in idle circuits. When a conventional sequential MTCMOS circuit transitions from the sleep mode to the active mode, significant bouncing noise is produced on the power and ground distribution networks. The reliability of the surrounding active circuitry is seriously degraded. A dynamic forward body bias technique is proposed in this paper to alleviate the ground bouncing noise in sequential MTCMOS circuits without sacrificing the data retention capability. With the new dynamic forward body bias technique, the peak ground bouncing noise is reduced by up to 91.70% as compared to the previously published sequential MTCMOS circuits in a UMC 80 nm CMOS technology. The design tradeoffs among important design metrics such as ground bouncing noise, leakage power consumption, active power consumption, data stability, and area are evaluated.