scholarly journals Characteristics of MPSoC Based On Dual Feedback Edge Triggered Flip Flop

2021 ◽  
Author(s):  
Satyaraj D ◽  
Bhanumathi V
Keyword(s):  
Processing System ◽  
Input Voltage ◽  
High Energy ◽  
Digital Data ◽  
Primary Concern ◽  
Flip Flop ◽  
Sram Cell ◽  
Digital Hardware ◽  
Bouncing Noise ◽  
Triggering Process

Abstract With the persistent scaling of semiconductor technology, the embedded multi-processor platforms lifetime reliability has been the primary concern for the industry. The advancements in technology permit several microprocessors integration, dedicated digital hardware, and at times mixed-signal circuits on a single silicon die, specifically multi-processor system-on-a-chip (MPSoC). In this paper, the design and analysis of CMOS based MPSoC is made. A CMOS based MPSoC is designed with 45nm technology. In this design, ADC converter is used in which 10-bit data is given as input, and are converted into digital data. A double feedback edge triggered flip flop is designed. The implementation of flip flop, based on both feedback and triggering process, is more effective in the elimination of error occurrence. Power Gating (PG) technique is proposed which exploits the stacking effect to achieve high energy efficiency. Binary controlled stacked SRAM cell, based on a parallel cross-coupling feedback controller, is implemented to reduce the leakage loss and ground bouncing noise. An inverter, based on NMOS and CMOS, is used for the inverting process. The input voltage of 5v is given and is varied. Then, a 2-bit counter is employed, which is responsible for counting down or counting up. The counter should count down if the signal is high. The counter should count up, if the signal is low. Thus, this design will be helpful in the implementation of compact processing system which may also be employed for many real-time applications where there is a need of compact device. The benefits of this multi processors integration will be helpful in speeding the process thereby reducing the leakage power loss, power consumption, delay factor and so on. The analysis of performance is carried out using CMOS based Tanner EDA, and the outcomes are represented.

scholarly journals Utilization of Power Gating Technique for the Analysis of MPSoC Based On Dual Feedback Edge Triggered Flip Flop

2021 ◽  
Author(s):  
Satyaraj D ◽  
Bhanumathi V
Keyword(s):  
Processing System ◽  
Input Voltage ◽  
High Energy ◽  
Digital Data ◽  
Primary Concern ◽  
Power Gating ◽  
Flip Flop ◽  
Sram Cell ◽  
Bouncing Noise ◽  
Triggering Process

Abstract With the persistent scaling of semiconductor technology, the embedded multi-processor platforms lifetime reliability has been the primary concern for the industry. The advancements in technology permit several microprocessors integration, dedicated digital hardware, and at times mixed-signal circuits on a single silicon die, specifically multi-processor system-on-a-chip (MPSoC). In this paper, the design and analysis of CMOS based MPSoC is made. A CMOS based MPSoC is designed with 45nm technology. In this design, ADC converter is used in which 10-bit data is given as input, and are converted into digital data. A double feedback edge triggered flip flop is designed. The implementation of flip flop, based on both feedback and triggering process, is more effective in the elimination of error occurrence. Power Gating (PG) technique is proposed which exploits the stacking effect to achieve high energy efficiency. Binary controlled stacked SRAM cell, based on a parallel cross-coupling feedback controller, is implemented to reduce the leakage loss and ground bouncing noise. An inverter, based on NMOS and CMOS, is used for the inverting process. The input voltage of 5v is given and is varied. Then, a 2-bit counter is employed, which is responsible for counting down or counting up. The counter should count down if the signal is high. The counter should count up, if the signal is low. Thus, this design will be helpful in the implementation of compact processing system which may also be employed for many real-time applications where there is a need of compact device. The benefits of this multi processors integration will be helpful in speeding the process thereby reducing the leakage power loss, power consumption, delay factor and so on. The analysis of performance is carried out using CMOS based Tanner EDA, and the outcomes are represented.

Quantitative Electron Microscope with imaging plate

1994 ◽  
Vol 52 ◽  
pp. 408-409
Author(s):  
D. Shindo
Keyword(s):  
Electron Microscope ◽  
Dynamic Range ◽  
Processing System ◽  
Digital Data ◽  
Imaging Plate ◽  
Crystal Thickness ◽  
X Ray Diffraction ◽  
Resolution Electron ◽  
Electron Intensity ◽  
Diffraction Patterns

Imaging plate has good properties, i.e., a wide dynamic range and good linearity for the electron intensity. Thus the digital data (2048x1536 pixels, 4096 gray levels in log scale) obtained with the imaging plate can be used for quantification in electron microscopy. By using the image processing system (PIXsysTEM) combined with a main frame (ACOS3900), quantitative analysis of electron diffraction patterns and high-resolution electron microscope (HREM) images has been successfully carried out.In the analysis of HREM images observed with the imaging plate, quantitative comparison between observed intensity and calculated intensity can be carried out by taking into account the experimental parameters such as crystal thickness and defocus value. An example of HREM images of quenched Tl2Ba2Cu1Oy (Tc = 70K) observed with the imaging plate is shown in Figs. 1(b) - (d) comparing with a structure model proposed by x-ray diffraction study of Fig. 1 (a). The image was observed with a JEM-4000EX electron microscope (Cs =1.0 mm).

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

Low Noise EEG Amplifier Board for Low Cost Wearable BCI Devices

2016 ◽  
Vol 5 (2) ◽  
pp. 17-28
Author(s):  
Ravim ◽  
Suma K. V.
Keyword(s):  
Noise Reduction ◽  
Digital Signal Processor ◽  
Low Cost ◽  
Processing System ◽  
Digital Signal ◽  
Low Noise ◽  
Digital Data ◽  
Signal Processing System ◽  
Analog To Digital ◽  
Reduction Techniques

Designing a real-time BCI device requires an Electroencephalogram (EEG) acquisition system and a signal processing system to process that acquired data. EEG acquisition boards available in market are expensive and they are required to be connected to computer for any processing work. Various low cost Digital Signal Processor (DSP) boards available in market come with internal Analog to Digital converters and peripheral interfaces. The idea is to design a low cost EEG amplifier board that can be used with these commercially available DSP boards. The analog data from EEG amplifier can be converted to digital data by DSP board and sent to computer via an interface for algorithm development and further control operations. EEG amplifiers are highly affected by noise from environment. Proper noise reduction techniques are implemented and simulated in circuit design. Each filter stage and noise reduction circuit is evaluated for a low noise design.

The digital data processing system of the ASTRO-E hard X-ray detector

1999 ◽  
Vol 320 (4-5) ◽  
pp. 377-377 ◽  
Author(s):  
Y. Terada ◽  
M. Tashiro ◽  
T. Takahashi ◽  
Y. Fukazawa ◽  
G. Kawaguchi ◽  
...  
Keyword(s):  
Data Processing ◽  
Processing System ◽  
Digital Data ◽  
Data Processing System ◽  
X Ray ◽  
Digital Data Processing

Direct Measurement of Electron Drift Parameters using Depth Sensing Single Carrier CdZnTe Detectors

1997 ◽  
Vol 487 ◽  
Author(s):  
Z. He ◽  
G. F. Knoll ◽  
D. K. Wehe ◽  
Y. F. Du
Keyword(s):  
Drift Time ◽  
Wide Band ◽  
High Energy ◽  
Digital Data ◽  
Depth Sensing ◽  
Single Carrier ◽  
Analysis System ◽  
Cdznte Detectors ◽  
Data Analysis System ◽  
Carrier Charge

AbstractThis paper describes some novel techniques developed for directly measuring the electron mobility μe and mean free drift time Te in wide band gap semiconductors. These methods are based on a newly-developed digital data analysis system, in conjunction with single carrier charge sensing and depth sensing techniques. Compared with conventional methods, the new techniques are easier to implement, do not involve curve fitting, allow the use of high energy γ-rays and are not sensitive to variations in pulse rise time.

Current Status of an On-Line Computer Data Processing System for High Energy Counter and Spark Chamber Experiments

1965 ◽  
Vol 12 (4) ◽  
pp. 222-223 ◽  
Author(s):  
K. J. Foley ◽  
R. S. Jones ◽  
S. J. Lindenbaum ◽  
W. A. Love ◽  
S. Ozaki ◽  
...  
Keyword(s):  
Data Processing ◽  
Processing System ◽  
High Energy ◽  
Current Status ◽  
Data Processing System ◽  
Computer Data ◽  
On Line ◽  
Computer Data Processing

Electronic Speckle Pattern Interferometry of the Vibrating Larynx

1995 ◽  
Vol 104 (1) ◽  
pp. 5-12 ◽  
Author(s):  
Glendon M. Gardner ◽  
Michelle Conerty ◽  
James Castracane ◽  
Steven M. Parnes
Keyword(s):  
Real Time ◽  
Quantitative Research ◽  
Speckle Pattern ◽  
Three Dimensional ◽  
Vocal Folds ◽  
Digital Data ◽  
Electronic Speckle Pattern Interferometry ◽  
Clinical Tool ◽  
Digital Hardware ◽  
Laser Holography

Laser holography is a technique that creates a three-dimensional image of a static object. This technique can be applied to the analysis of vibrating structures. Electronic speckle pattern interferometry uses a laser for illumination of the vibrating object and solid state detectors and digital hardware technology for capturing and processing the image in real time. This was performed on a human cadaver larynx and is the first time an interferogram of vibrating vocal cords has ever been obtained. Dark and bright interference fringes are seen that represent the vibratory motion of the vocal folds. These are presented in still photos as well as real-time on videotape. This method can provide advantages over current techniques of laryngeal study: it is sensitive to motion in the vertical dimension, and the digital data can be quantitatively analyzed. Application of this technique to study the larynx should eventually be a valuable clinical tool and provide quantitative research data.

scholarly journals Hardware Implementation Study of Particle Tracking Algorithm on FPGAs

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2546
Author(s):  
Alessandro Gabrielli ◽  
Fabrizio Alfonsi ◽  
Alberto Annovi ◽  
Alessandra Camplani ◽  
Alessandro Cerri
Keyword(s):  
High Speed ◽  
High Performance ◽  
Hardware Implementation ◽  
High Energy Physics ◽  
Medical Image Analysis ◽  
Computation Time ◽  
High Energy ◽  
Spatial Transformation ◽  
Flip Flop ◽  
Energy Physics

In recent years, the technological node used to implement FPGA devices has led to very high performance in terms of computational capacity and in some applications these can be much more efficient than CPUs or other programmable devices. The clock managers and the enormous versatility of communication technology through digital transceivers place FPGAs in a prime position for many applications. For example, from real-time medical image analysis to high energy physics particle trajectory recognition, where computation time can be crucial, the benefits of using frontier FPGA capabilities are even more relevant. This paper shows an example of FPGA hardware implementation, via a firmware design, of a complex analytical algorithm: The Hough transform. This is a mathematical spatial transformation used here to facilitate on-the-fly recognition of the trajectories of ionising particles as they pass through the so-called tracker apparatus within high-energy physics detectors. This is a general study to demonstrate that this technique is not only implementable via software-based systems, but can also be exploited using consumer hardware devices. In this context the latter are known as hardware accelerators. In this article in particular, the Xilinx UltraScale+ FPGA is investigated as it belongs to one of the frontier family devices on the market. These FPGAs make it possible to reach high-speed clock frequencies at the expense of acceptable energy consumption thanks to the 14 nm technological node used by the vendor. These devices feature a huge number of gates, high-bandwidth memories, transceivers and other high-performance electronics in a single chip, enabling the design of large, complex and scalable architectures. In particular the Xilinx Alveo U250 has been investigated. A target frequency of 250 MHz and a total latency of 30 clock periods have been achieved using only the 17 ÷ 53% of LUTs, the 8 ÷ 12% of DSPs, the 1 ÷ 3% of Block Rams and a Flip Flop occupancy range of 9 ÷ 28%.

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