Coordinated ramp signal optimization framework based on time series flux-correlation analysis

Urban expressways provide an effective solution to traffic congestion, and ramp signal optimization can ensure the efficiency of expressway traffic. The existing methods are mainly based on the static spatial distance between mainline and ramp to achieve multi-ramp coordinated signal optimization, which lacks the consideration of the dynamic traffic flow and lead to the long time-lag, thus affecting the efficiency. This article develops a coordinated ramp signal optimization framework based on mainline traffic states. The main contribution was traffic flow-series flux-correlation analysis based on cross-correlation, and development of a novel multifactorial matric that combines flow-correlation to assign the excess demand for mainline traffic. Besides, we used the GRU neural network for traffic flow prediction to ensure real-time optimization. To obtain a more accurate correlation between ramps and congested sections, we used gray correlation analysis to determine the percentage of each factor. We used the Simulation of Urban Mobility simulation platform to evaluate the performance of the proposed method under different traffic demand conditions, and the experimental results show that the proposed method can reduce the density of mainline bottlenecks and improve the efficiency of mainline traffic.

An Opamp-Less PVT Compensation Structure for Ramp Generator Circuit

Accurate ramp signal, with low power dissipation, is highly demanded, for applications like counter ADC. This paper presents a novel low power ramp generator circuit with a negative feedback loop for compensation of the variations in process, voltage, and temperature (PVT). While using an opamp for PVT compensation has been essential in the previous ramp generator structures, the proposed ramp generator is opamp-less. Derived equations of the proposed ramp generator circuit show that PVT compensation structure works effectively. In addition, the circuit design and simulations were done in TSMC 0.18[Formula: see text][Formula: see text]m CMOS technology. Corner analysis shows that integral non-linearity (INL) of the ramp signal is about 3.7[Formula: see text]mV, for a wide temperature range, while the power dissipation of the circuit is about 1.16[Formula: see text][Formula: see text]W.

Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation

This paper presents the design of linear ramp generator and digital BIST for an on-chip ADC testing. It replaces the costly and time-consuming traditional mixed signal test methods like DSP-based testing, ATE, etc. The proposed on-chip analog ramp generator uses only a few transistors to generate linear ramp signal. A TIQ comparator based 8-bit flash ADC is taken under test. The output response of the ADC is analyzed in the digital BIST to measure the primary nonidealities affecting the linearity and accuracy of the data conversion. In testing, ADC generates the digital data sequence as a test pattern in response to the ramp input while digital BIST estimates the conversion error. This method does not require DAC and any additional components which increase the area overhead of ADC test. The complete design of ramp generator is integrated with TIQ flash ADC and verified in 0.18[Formula: see text][Formula: see text]m CMOS technology with 1.8[Formula: see text]V of the power supply and 100[Formula: see text]kHz of the input frequency. Measurement of nonidealities shows that the design of an 8-bit flash ADC has good accuracy in data conversion with the differential nonlinearity of [Formula: see text]0.24/[Formula: see text]0.17[Formula: see text]LSB and integral nonlinearity of [Formula: see text]0.44/[Formula: see text]0.04[Formula: see text]LSB.

Fuzzy LPCM controlled buck integrated PFC convert-er for Class-C&D appliances

This propounded a novel method of design and implementation of a fuzzy linear peak current mode (LPCM) controlled Buck Integrated Power Factor Correction (PFC) Converter. It derives its advantages through low buck capacitor voltage and single control switch, which leads to reduced complex control and price. Sub-harmonic oscillations generates in peak current controller can be nullified by using ramp signal, there by improves the overall performance of the converter. The fuzzy controller (FLC) robust and effective than conventional linear controllers like P, PI, PID, hence in this work a (90 – 265V), 50Hz AC, 48V DC and 100 kHz frequency converter is implemented in MATLAB/Simulink software and results are verified experimentally. Results show that converter meets international regularity commission regulations.

Fuzzy peak current controlled integrated PFC convert-er with slope compensation

This propounded a novel method of design and implementation of a fuzzy peak current mode (PCM) controlled Buck Integrated Power Factor Correction (PFC) Converter with compensation ramp. It derives its advantages through low buck capacitor voltage and single control switch, which leads to reduced complex control and price. Sub-harmonic oscillations generates in peak current controller can be nullified by using ramp signal, there by improves the overall performance of the converter. The fuzzy controller (FLC) robust and effective than conventional linear controllers like P, PI, PID, hence in this work a (90 – 265V), 50Hz AC, 48V DC and 100 kHz frequency converter is implemented in MATLAB/Simulink software and results are presented. Results show that converter meets international regularity commission regulations.