Estimation of Single Event Transient Voltage Pulses in VLSI Circuits From Heavy-Ion-Induced Transient Currents Measured in a Single MOSFET

In a triple-well NMOSFET, a deep n+ well (DNW) is buried in the substrate to isolate the substrate noise. The presence of this deep n+ well leads to changes in single-event transient effects compared to bulk NMOSFET. In space, a single cosmic particle can deposit enough charge in the sensitive volume of a semiconductor device to cause a potential change in the transient state, that is, a single-event transient (SET). In this study, a quantitative characterization of the effect of a DNW on a SET in a 65 nm triple-well NMOSFET was performed using heavy ion experiments. Compared with a bulk NMOSFET, the experimental data show that the percentages of average increase of a SET pulse width are 22% (at linear energy transfer (LET) = 37.4 MeV·cm2/mg) and 23% (at LET = 22.2 MeV·cm2/mg) in a triple-well NMOSFET. This study indicates that a triple-well NMOSFET is more sensitive to a SET, which means that it may not be appropriate for radiation hardened integrated circuit design compared with a bulk NMOSFET.

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Single-Event Transient Measurements on a DC/DC Pulse Width Modulator Using Heavy Ion, Proton, and Pulsed Laser

Journal of Electronic Testing ◽

10.1007/s10836-013-5431-7 ◽

2014 ◽

Vol 30 (1) ◽

pp. 149-154 ◽

Cited By ~ 3

Author(s):

Y. Ren ◽

A.-L. He ◽

S.-T. Shi ◽

G. Guo ◽

L. Chen ◽

...

Keyword(s):

Pulse Width ◽

Pulsed Laser ◽

Heavy Ion ◽

Single Event ◽

Single Event Transient ◽

Pulse Width Modulator ◽

Ion Proton ◽

Transient Measurements

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Study of single event transient induced by heavy‐ion in NMOS transistor and CMOS inverter

Concurrency and Computation Practice and Experience ◽

10.1002/cpe.4802 ◽

2018 ◽

Vol 31 (12) ◽

Author(s):

Cheng Gao ◽

Rui Zhang ◽

Jiaoying Huang ◽

Chengcheng Fu

Keyword(s):

Heavy Ion ◽

Single Event ◽

Single Event Transient ◽

Cmos Inverter ◽

Nmos Transistor

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Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

Aerospace ◽

10.3390/aerospace7020012 ◽

2020 ◽

Vol 7 (2) ◽

pp. 12 ◽

Cited By ~ 1

Author(s):

Ygor Q. Aguiar ◽

Frédéric Wrobel ◽

Jean-Luc Autran ◽

Paul Leroux ◽

Frédéric Saigné ◽

...

Keyword(s):

System Integration ◽

Space Station ◽

Vlsi Circuits ◽

Advanced Technology ◽

Combinational Circuits ◽

Single Event ◽

Single Event Transient ◽

Space Applications ◽

Predictive Assessment ◽

Technology Nodes

Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event Transient (SET) effects were considered irrelevant compared to the data rupture caused by Single-Event Upset (SEU) effects. However, the importance of considering SET in Very-Large-System-Integration (VLSI) circuits increases given the reduction of the transistor dimensions and the logic data path depth in advanced technology nodes. Accordingly, the threat of SET in electronics systems for space applications must be carefully addressed along with the SEU characterization. In this work, a systematic prediction methodology to assess and improve the SET immunity of digital circuits is presented. Further, the applicability to full-custom and cell-based design methodologies are discussed, and an analysis based on signal probability and pin assignment is proposed to achieve a more application-efficient SET-aware optimization of synthesized circuits. For instance, a SET-aware pin assignment can provide a reduction of 37% and 16% on the SET rate of a NOR gate for a Geostationary Orbit (GEO) and the International Space Station (ISS) orbit, respectively.

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