Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process

2016 ◽  
Vol 45 (6) ◽  
pp. 851-858 ◽  
Author(s):  
Yuan Wang ◽  
Yuequan Liu ◽  
Song Jia ◽  
Xing Zhang
Keyword(s):  
Clock And Data Recovery ◽  
Data Recovery ◽  
Cmos Process ◽  
Operating Range ◽  
Delay Locked Loop ◽  
Low Jitter ◽  
Wide Operating

scholarly journals A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 177
Author(s):  
Dongjun Park ◽  
Sungwook Choi ◽  
Jongsun Kim
Keyword(s):  
Sampling Technique ◽  
Cmos Process ◽  
Detection Range ◽  
Delay Locked Loop ◽  
Delta Sigma Modulator ◽  
Correlated Double Sampling ◽  
Delta Sigma ◽  
Fast Power ◽  
Low Jitter ◽  
Reference Clock

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

Low-jitter design method based on n-domain jitter analysis for 10 Gbit/s clock and data recovery ICs

2009 ◽  
Vol 45 (16) ◽  
pp. 808 ◽  
Author(s):  
K. Kishine ◽  
H. Inaba ◽  
Ma. Nakamura ◽  
Mi. Nakamura ◽  
Y. Ohtomo ◽  
...  
Keyword(s):  
Design Method ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Low Jitter

scholarly journals Design and Implementation of Low Power Delay Locked Loop using Multiplexer Based Phase Frequency Detector

2020 ◽  
Vol 9 (5) ◽  
pp. 951-955
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Clock Recovery ◽  
Clock Frequency ◽  
Phase Frequency Detector ◽  
Delay Locked Loop ◽  
Design And Implementation ◽  
Frequency Detector

This paper proposes design and implementation of low power Delay Locked Loop Architecture, with dynamic Multiplexer based Phase Frequency Detector with minimum locking time. Clock and data recovery systems are employed to derive the clocking information to correctly decode the transmitted data at the receiver. Delay Locked Loop is one of the most important clock recovery systems. The DLL architecture is designed using Cadence Virtuoso 180nm Technology with 1.8V power supply. The proposed DLL with Multiplexer based phase frequency detector shows significant reduction in power dissipation by 10% compared to DLL designed using D-FF based PFD and achieves locking state within 10 clock cycles with minimum jitter of 4.84326ps, measured within clock frequency range of 100-250MHz.

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

2015 ◽  
Vol 50 (11) ◽  
pp. 2603-2612 ◽  
Author(s):  
Sang-Hyeok Chu ◽  
Woorham Bae ◽  
Gyu-Seob Jeong ◽  
Sungchun Jang ◽  
Sungwoo Kim ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Data Recovery ◽  
Cmos Process ◽  
Digital Clock
Sign in / Sign up

Export Citation Format

Share Document