scholarly journals 27.2: Invited Paper: Towards High Performance Gate Electrodes: Resistance Reduction in Molybdenum Films by Seed Layer Application

2021 ◽  
Vol 52 (S1) ◽  
pp. 170-174
Author(s):  
Hennrik Schmidt ◽  
Harald Koestenbauer ◽  
Dominik Lorenz ◽  
Christian Linke ◽  
Enrico Franzke ◽  
...  
Keyword(s):  
Seed Layer ◽  
High Performance ◽  
Gate Electrodes ◽  
Resistance Reduction

Optimization of the Hybrid Ship Transport Factor through Retrofitted Wave Cancelling Side-Hull Expansions and Bow Bulb

2015 ◽  
Author(s):  
Manivannan Kandasamy ◽  
Ping C. Wu ◽  
Scott Bartlett ◽  
Loc Nguyen ◽  
Frederick Stern
Keyword(s):  
High Performance ◽  
Negative Impact ◽  
Fiscal Year ◽  
Hull Form ◽  
Transport Factor ◽  
Resistance Reduction ◽  
The Us ◽  
Us Navy ◽  
Speed Range ◽  
Design Speed

The US Navy is currently considering the introduction of a Flight III variant beginning with DDG-123 in Fiscal Year 2016. The new design incorporates a new combat system and associated power and cooling upgrades. The overall system improvements increase the payload of the ship and the resulting increased displacement has a negative impact on the service life allowance for range, fuel consumption and sea-keeping characteristics. The present objective is to increase the hull displacement without resistance and sea-keeping penalty and with minimal modifications to the baseline DTMB-5415 design (open literature surrogate of the existing DDG-51 hull form) by using retrofitted blisters in the form of side hull expansions and a bow-bulb. The investigation makes use of high-performance CFD computing for analysis of wave cancellation mechanisms. A candidate modified 5415 design with both blisters and bow bulb shows a resistance reduction of ~11% w.r.t.the baseline 5415 in the design speed range of 15-19 knots, even though the displacement is increased by 8%, such that the transport factor is increased by 19%.

Semi-additive Process Based Cu Wirings with Ultra Smooth Electroless Cu Seed Layer and Important Factor for High Frequency Transmission Property

2019 ◽  
Vol 2019 (1) ◽  
pp. 000409-000414
Author(s):  
Masaya Toba ◽  
Shuji Nomoto ◽  
Nobuhito Komuro ◽  
Kazuyuki Mitsukura ◽  
Shinichiro Abe ◽  
...  
Keyword(s):  
Seed Layer ◽  
High Performance ◽  
Printed Circuit Boards ◽  
Peel Strength ◽  
60 Ghz ◽  
Circuit Boards ◽  
Additive Process ◽  
Seed Formation ◽  
Anchoring Effect ◽  
Semiconductor Packages

Abstract Semiconductor packages for high performance devices with printed circuit boards having multi wiring layers such as FC-BGA have been attracting the attention in order to realize ultra-reliable and low latency communications in 5G networking. Cu wirings for the package are usually fabricated by via formation by laser for dielectric, desmear, electroless Cu seed formation, photoresist patterning, electrolytic Cu plating, resist stripping and seed layer etching. Though a desmear process can obtain enough adhesion between dielectric and Cu seed layer by anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of a desmear process, we applied an UV modification for the surface of dielectric in order to realize a smooth and high adhesive seed layer against dielectric. We obtained 0.8 kN/m of peel strength between dielectric and Cu seed layer in spite of surface roughness (Ra) of dielectric was 45 nm by nano-level anchoring effect at UV modified layer. Due to the smooth interface by UV modification, S21 value of microstrip line was 26 % improved compared to that assembled through desmear process at 60 GHz.

High Performance Organic Field-Effect Transistors and Integrated Inverters

2001 ◽  
Vol 665 ◽  
Author(s):  
A. Ullmann ◽  
J. Ficker ◽  
W. Fix ◽  
H. Rost ◽  
W. Clemens ◽  
...  
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Drain Current ◽  
Organic Field Effect Transistors ◽  
Metal Contacts ◽  
Gate Electrodes ◽  
Polymer Semiconductors ◽  
Set Up

ABSTRACTIntegrated plastic circuits (IPCs) will become an integral component of future low cost electronics. For low cost processes IPCs have to be made of all-polymer Transistors. We present our recent results on fabrication of Organic Field-Effect Transistors (OFETs) and integrated inverters. Top-gate transistors were fabricated using polymer semiconductors and insulators. The source-drain structures were defined by standard lithography of Au on a flexible plastic film, and on top of these electrodes, poly(3-alkylthiophene) (P3AT) as semiconductor, and poly(4-hydroxystyrene) (PHS) as insulator were homogeneously deposited by spin-coating. The gate electrodes consist of metal contacts. With this simple set-up, the transistors exhibit excellent electric performance with a high source-drain current at source - drain and gate voltages below 30V. The characteristics show very good saturation behaviour for low biases and are comparable to results published for precursor pentacene. With this setup we obtain a mobility of 0.2cm2/Vs for P3AT. Furthermore, we discuss organic integrated inverters exhibiting logic capability. All devices show shelf-lives of several months without encapsulation.

scholarly journals Assembly of Cu Wirings with Ultrasmooth and High-Adhesive Electroless Cu Seed Layer by Using UV Modification and Low Attenuation of High-Frequency Transmission Property

2020 ◽  
Vol 17 (2) ◽  
pp. 45-51
Author(s):  
Masaya Toba ◽  
Shuji Nomoto ◽  
Nobuhito Komuro ◽  
Kazuyuki Mitsukura ◽  
Shinichiro Abe ◽  
...  
Keyword(s):  
Seed Layer ◽  
High Performance ◽  
Flip Chip ◽  
Printed Circuit Boards ◽  
Peel Strength ◽  
60 Ghz ◽  
Circuit Boards ◽  
Seed Formation ◽  
Anchoring Effect ◽  
Semiconductor Packages

Abstract Semiconductor packages for high-performance devices with printed circuit boards having multiwiring layers such as flip-chip ball grid array have been attracting the attention to realize ultrare-liable and low-latency communications in 5G networking. Cu wirings for the package are usually fabricated by via formation by laser for dielectric, desmear, electroless Cu seed formation, photoresist patterning, electrolytic Cu plating, resist stripping, and seed layer etching. Although a desmear process can obtain enough adhesion between dielectric and Cu seed layer by anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of a desmear process, we applied a UV modification for the surface of dielectric to realize a smooth and high-adhesive seed layer against dielectric. We obtained .8 kN/m of peel strength between dielectric and Cu seed layer in spite of surface roughness of the dielectric being 45 nm by a nanolevel anchoring effect at the UV-modified layer. Because of the smooth interface by UV modification, the S21 value of microstrip line was 26% improved compared with that assembled through the desmear process at 60 GHz.

High-Performance ZnO Nanowire Transistors with Aluminum Top-Gate Electrodes and Naturally Formed Hybrid Self-Assembled Monolayer/AlOx Gate Dielectric

ACS Nano ◽  
2014 ◽  
Vol 8 (7) ◽  
pp. 6840-6848 ◽  
Author(s):  
Daniel Kälblein ◽  
Hyeyeon Ryu ◽  
Frederik Ante ◽  
Bernhard Fenk ◽  
Kersten Hahn ◽  
...  
Keyword(s):  
High Performance ◽  
Gate Dielectric ◽  
Zno Nanowire ◽  
Self Assembled Monolayer ◽  
Nanowire Transistors ◽  
Gate Electrodes ◽  
Self Assembled

High performance ZnO nanowire field effect transistor using self-aligned nanogap gate electrodes

2006 ◽  
Vol 89 (26) ◽  
pp. 263102 ◽  
Author(s):  
S. N. Cha ◽  
J. E. Jang ◽  
Y. Choi ◽  
G. A. J. Amaratunga ◽  
G. W. Ho ◽  
...  
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Zno Nanowire ◽  
Gate Electrodes ◽  
Effect Transistor

Bumping Process Impact on the Chip Package Interaction (CPI) Reliability

2018 ◽  
Vol 2018 (1) ◽  
pp. 000270-000276 ◽  
Author(s):  
Lei Fu ◽  
Milind Bhagavat ◽  
Ivor Barber
Keyword(s):  
Integrated Circuit ◽  
Seed Layer ◽  
High Performance ◽  
Flip Chip ◽  
Leading Edge ◽  
Lead Free ◽  
Assembly Process ◽  
Chip Technology ◽  
Layer Deposition ◽  
Ic Package

Abstract Flip chip technology is widely used in advanced integrated circuit (IC) package. Chip package interaction (CPI) became critical in flip chip technology that needed to be addressed to avoid electrical or mechanical failure in products. When addressing CPI challenges, different areas have to be considered, ranging from silicon BEOL design and processing, bumping design and process, package assembly process, assembly bill of material (BOM), and substrate technology. Controlled collapse chip connection (C4) bump technology provided the inter-connection between the IC to package substrate for high-performance, leading-edge microprocessors. It is very critical for chip package interaction (CPI). With the transfer to lead free technology, bumping process plays more and more important role for chip package interaction reliability. In this paper, we focused on bumping process effect on the CPI reliability. The bumping process has been reviewed and CPI reliability issues induced by the bumping process like particles, Ti seed layer deposition, UBM undercut, Cu pad oxidation and contamination, photoresist opening damage have been discussed. Bumping process optimization and corrective actions have been taken to reduce those defects and improve CPI reliability.

Electroless Plating with UV Modification for Thermosetting Dielectric and Decay Suppression of High Frequency Transmission Property

2020 ◽  
Vol 2020 (1) ◽  
pp. 000174-000180
Author(s):  
Masaya Toba ◽  
Kazuyuki Mitsukura ◽  
Masaki Yamaguchi
Keyword(s):  
Surface Roughness ◽  
Seed Layer ◽  
High Performance ◽  
Printed Circuit Boards ◽  
Peel Strength ◽  
Circuit Boards ◽  
Additive Process ◽  
Anchoring Effect ◽  
Cu Film ◽  
Semiconductor Packages

Abstract Semiconductor packages for high performance devices with printed circuit boards having multi wiring layers such as FC-BGA have been attracting the attention in order to realize ultra-reliable and low latency communications in 5G networking. Cu wirings for the package are usually fabricated by semi-additive process (SAP) with desmear process and/or modified semi-additive process (MSAP) by using Cu film with large surface roughness. Though a desmear process and Cu film can obtain enough adhesion between dielectric and Cu seed layer by anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of that processes, we applied an UV modification for the surface of our developed thermosetting dielectric in order to realize a smooth and high adhesive seed layer against the dielectric. We obtained 0.5 kN/m of peel strength between dielectric and Cu seed layer in spite of surface roughness (Ra) of dielectric was 265 nm by nano-level anchoring effect at UV modified layer. Due to the smooth interface by UV modification, the normalized S21 value of microstrip line was about 29 % improved compared to that assembled through Cu film with Ra of 2400 nm at 50 GHz.

PEDOT gate electrodes with PVP/Al2O3 dielectrics for stable high-performance organic TFTs

2013 ◽  
Vol 9 (6) ◽  
pp. 741-746 ◽  
Author(s):  
Young Kyu Lee ◽  
Md. Maniruzzaman ◽  
Chiyoung Lee ◽  
Mi Jung Lee ◽  
Eun-Gu Lee ◽  
...  
Keyword(s):  
High Performance ◽  
Gate Electrodes
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