Bumping Process Impact on the Chip Package Interaction (CPI) Reliability

2018 ◽  
Vol 2018 (1) ◽  
pp. 000270-000276 ◽  
Author(s):  
Lei Fu ◽  
Milind Bhagavat ◽  
Ivor Barber
Keyword(s):  
Integrated Circuit ◽  
Seed Layer ◽  
High Performance ◽  
Flip Chip ◽  
Leading Edge ◽  
Lead Free ◽  
Assembly Process ◽  
Chip Technology ◽  
Layer Deposition ◽  
Ic Package

Abstract Flip chip technology is widely used in advanced integrated circuit (IC) package. Chip package interaction (CPI) became critical in flip chip technology that needed to be addressed to avoid electrical or mechanical failure in products. When addressing CPI challenges, different areas have to be considered, ranging from silicon BEOL design and processing, bumping design and process, package assembly process, assembly bill of material (BOM), and substrate technology. Controlled collapse chip connection (C4) bump technology provided the inter-connection between the IC to package substrate for high-performance, leading-edge microprocessors. It is very critical for chip package interaction (CPI). With the transfer to lead free technology, bumping process plays more and more important role for chip package interaction reliability. In this paper, we focused on bumping process effect on the CPI reliability. The bumping process has been reviewed and CPI reliability issues induced by the bumping process like particles, Ti seed layer deposition, UBM undercut, Cu pad oxidation and contamination, photoresist opening damage have been discussed. Bumping process optimization and corrective actions have been taken to reduce those defects and improve CPI reliability.

Manufacturing processes for fabrication of flip-chip micro-bumps used in microelectronic packaging: An overview

2019 ◽  
Vol 3 (1) ◽  
pp. 69-83 ◽  
Author(s):  
Madhav Datta
Keyword(s):  
Electronic Packaging ◽  
High Performance ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Void Formation ◽  
High Volume ◽  
Lead Free ◽  
Manufacturing Processes ◽  
Solder Paste ◽  
Chip Technology

Electronic packaging is the methodology for connecting and interfacing the chip technology with a system and the physical world. The objective of packaging is to ensure that the devices and interconnections are packaged efficiently and reliably. Chip–package interconnection technologies currently used in the semiconductor industry include wire bonding, tape automated bonding and flip-chip solder bump connection. Among these interconnection techniques, the flip-chip bumping technology is commonly used in advanced electronic packages since this interconnection is an area array configuration so that the entire surface of the chip can be covered with bumps for the highest possible input/output (I/O) counts. The present article reviews the manufacturing processes for the fabrication of flip-chip bumps for chip–package interconnection. Various solder bumping technologies used in high-volume production include evaporation, solder paste screening and electroplating. Evaporation process produces highly reliable bumps, but it is extremely expensive and is limited to lead or lead-rich solders. Solder paste screening is cost-effective, but issues related to excessive void formation limits the process to low-end products. On the other hand, electrochemical fabrication of flip-chip bumps is an extremely selective and efficient process, which is extendible to finer pitch, larger wafers and a variety of solder compositions, including lead-free alloys. Electrochemically fabricated copper pillar bumps offer fine pitch capabilities with excellent electromigration performance. Due to these virtues, the copper pillar bumping technology is emerging as a lead-free bumping technology option for high-performance electronic packaging.

Development of 3D System-in-Package with TSV Technology

2014 ◽  
Vol 2014 (1) ◽  
pp. 000612-000617 ◽  
Author(s):  
Shota Miki ◽  
Takaharu Yamano ◽  
Sumihiro Ichikawa ◽  
Masaki Sanada ◽  
Masato Tanaka
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Organic Substrate ◽  
Back Side ◽  
Final Thickness ◽  
Chip Technology ◽  
Type Semiconductor ◽  
Interconnect Reliability ◽  
Solder Balls ◽  
Carrier Wafer

In recent years, products such as smart phones, tablets, and wearable devices, are becoming miniaturized and high performance. 3D-type semiconductor structures are advancing as the demand for high-density assembly increases. We studied a fabrication process using a SoC die and a memory die for 3D-SiP (System in Package) with TSV technology. Our fabrication is comprised of two processes. One is called MEOL (Middle End of Line) for exposing and completing the TSV's in the SoC die, and the other is assembling the SoC and memory dice in a 3D stack. The TSV completion in MEOL was achieved by SoC wafer back-side processing. Because its final thickness will be a thin 50μm (typical), the SoC wafer (300 mm diameter) is temporarily attached face-down onto a carrier-wafer. Careful back-side grinding reveals the “blind vias” and fully opens them into TSV's. A passivation layer is then grown on the back of the wafer. With planarization techniques, the via metal is accessed and TSV pads are built by electro-less plating without photolithography. After the carrier-wafer is de-bonded, the thin wafer is sawed into dice. For assembling the 3D die stack, flip-chip technology by thermo-compression bonding was the method chosen. First, the SoC die with copper pillar bumps is assembled to the conventional organic substrate. Next the micro-bumps on the memory die are bonded to the TSV pads of the SoC die. Finally, the finished assembly is encapsulated and solder balls (BGA) are attached. The 3D-SiP has passed both package-level reliability and board-level reliability testing. These results show we achieved fabricating a 3D-SiP with high interconnect reliability.

Surface Energy and Wettability Study of Flip Chip Packaging Materials

2011 ◽  
Vol 2011 (1) ◽  
pp. 000961-000970
Author(s):  
Jinlin Wang
Keyword(s):  
Surface Energy ◽  
Flip Chip ◽  
Substrate Surface ◽  
Solid Surfaces ◽  
Energy Calculation ◽  
Assembly Process ◽  
Flip Chip Packaging ◽  
Materials Used ◽  
Lead Free Solders ◽  
Ic Package

The surface energy of solid surfaces and surface tension of liquids are important parameters in the IC package assembly process. Wettability analyses have been completed for various materials used in the assembly process of flip chip packages, including underfills, substrates, fluxes, and lead free solders. We will highlight some of these results in this paper. We will focus our discussion on substrate surface energy analysis. A brief discussion of different surface energy methods and the liquid selection criteria will be given. The advantage and limitation of the surface energy calculation methods will be discussed. The data from several case studies will be presented. Our results show that contact angle and surface energy measurements are very useful for quality control and product development where interfacial properties are important.

Robust Design Analysis on Fatigue Life of Lead-Free Sn0.5Ag Solder in a Multichip Module Package

2013 ◽  
Vol 284-287 ◽  
pp. 375-379 ◽  
Author(s):  
Chieh Kung
Keyword(s):  
Fatigue Life ◽  
Integrated Circuits ◽  
Robust Design ◽  
High Speed ◽  
Flip Chip ◽  
Design Analysis ◽  
Influential Factor ◽  
Fatigue Reliability ◽  
Chip Technology ◽  
Ic Package

System-in-package (SiP) has become a mainstream technology in IC package industry as it provides the solutions to the growing needs of high speed functions, mobility/portability, energy efficiency, and miniaturization of electronic products. One special form of SiP is the multi-chip module (MCM) in which multiple integrated circuits (ICs), semiconductor dies or other discrete components are packaged onto a unifying substrate. Thus, the reliability of package integrity becomes one of the major reliability concerns. In the present paper, a robust design analysis on the thermo-mechanical reliability of an MCM package with flip-chip technology is demonstrated. Our results show that for the specific package, the CTE of the substrate is the most influential factor to the fatigue reliability of the package. The optimal combination of the parameters is recommended. The robust design analysis optimizes the fatigue life from 165 cycles to 1080 cycles which is a 554.5% gain on the fatigue life.

High Reliability and Thermal Performance FCBGA Package

2007 ◽  
Author(s):  
Gino Hung ◽  
Ho-Yi Tsai ◽  
Chun An Huang ◽  
Steve Chiu ◽  
C. S. Hsiao
Keyword(s):  
Thermal Performance ◽  
High Performance ◽  
Flip Chip ◽  
Dielectric Material ◽  
High Reliability ◽  
Lead Free ◽  
Molding Process ◽  
Molding Compound ◽  
Reliability Performance ◽  
Low K

A high reliability and high thermal performance molding flip chip ball grid arrays structure which was improved from Terminator FCBGA®. (The structure are shown as Fig. 1) It has many advantages, like better coplanarity, high through put (multi pes for each shut of molding process), low stress, and high thermal performance. In conventional flip chip structure, underfill dispenses and cure processes are a bottleneck due to low through put (dispensing unit by unit). For the high performance demand, large package/die size with more integrated functions needs to meet reliability criteria. Low k dielectric material, lead free bump especially and the package coplanarity are also challenges for package development. Besides, thermal performance is also a key concern with high power device. From simulation and reliability data, this new structure can provide strong bump protection and reach high reliability performance and can be applied for low-K chip and all kind of bump composition such as tin-lead, high lead, and lead free. Comparing to original Terminator FCBGA®, this structure has better thermal performance because the thermal adhesive was added between die and heat spreader instead of epoxy molding compound (EMC). The thermal adhesive has much better thermal conductivity than EMC. Furthermore, this paper also describes the process and reliability validation result.

scholarly journals Assembly of Cu Wirings with Ultrasmooth and High-Adhesive Electroless Cu Seed Layer by Using UV Modification and Low Attenuation of High-Frequency Transmission Property

2020 ◽  
Vol 17 (2) ◽  
pp. 45-51
Author(s):  
Masaya Toba ◽  
Shuji Nomoto ◽  
Nobuhito Komuro ◽  
Kazuyuki Mitsukura ◽  
Shinichiro Abe ◽  
...  
Keyword(s):  
Seed Layer ◽  
High Performance ◽  
Flip Chip ◽  
Printed Circuit Boards ◽  
Peel Strength ◽  
60 Ghz ◽  
Circuit Boards ◽  
Seed Formation ◽  
Anchoring Effect ◽  
Semiconductor Packages

Abstract Semiconductor packages for high-performance devices with printed circuit boards having multiwiring layers such as flip-chip ball grid array have been attracting the attention to realize ultrare-liable and low-latency communications in 5G networking. Cu wirings for the package are usually fabricated by via formation by laser for dielectric, desmear, electroless Cu seed formation, photoresist patterning, electrolytic Cu plating, resist stripping, and seed layer etching. Although a desmear process can obtain enough adhesion between dielectric and Cu seed layer by anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of a desmear process, we applied a UV modification for the surface of dielectric to realize a smooth and high-adhesive seed layer against dielectric. We obtained .8 kN/m of peel strength between dielectric and Cu seed layer in spite of surface roughness of the dielectric being 45 nm by a nanolevel anchoring effect at the UV-modified layer. Because of the smooth interface by UV modification, the S21 value of microstrip line was 26% improved compared with that assembled through the desmear process at 60 GHz.

Next-Generation Copper, Nickel and Lead-Free Metallization Products for Next-Generation Devices and Applications

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000611-000638
Author(s):  
Jonathan Prange ◽  
Yi Qin ◽  
Matthew Thorseth ◽  
Inho Lee ◽  
Masaaki Imanari ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Lead Free ◽  
Lead Free Solder ◽  
Next Generation ◽  
Copper Nickel ◽  
Microelectronic Devices ◽  
Architectural Features ◽  
Free Solder

Flip-chip interconnect and 3-D packaging applications must utilize reliable, high-performance metallization products in order to produce highly-efficient, low-cost microelectronic devices. As the market moves to shrinking device architectural features and increasingly difficult pattern layouts, more demand is placed on the plating performance of the copper, nickel and lead-free solder products used to create these interconnects. Additionally, the move from traditional C4 bumping processes with lead-free solder to capping processes utilizing copper pillars with lead-free solder requires metal interfaces that are highly compatible in order to avoid defects that could occur. In this paper, next-generation products developed for copper pillar, nickel barrier, and lead-free solder plating will be introduced that are capable of delivering high-performance and highly reliable metallic interconnects. The additive packages that were selected and optimized allowing for increased rate of electrodeposition, uniform height control with controllable pillar shape and smooth surface morphology will be discussed. Furthermore, compatibility will be shown for a lead-free solder cap electrodeposited onto copper pillar structures, both with and without nickel barrier layers, on large pore features (≥50 μm diameter) and micro pore features (≤20 μm diameter) for both bumping and capping applications.

Large Die Size Lead Free Flip Chip Ball Grid Array Packaging Considerations for 40nm Fab Technology

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000570-000585
Author(s):  
Mark A. Bachman ◽  
Jerry Liao ◽  
John Osenbach ◽  
Zafer Kutlu ◽  
Jaeyun Gim ◽  
...  
Keyword(s):  
Flip Chip ◽  
Leading Edge ◽  
Ball Grid Array ◽  
Lead Free ◽  
Production Lines ◽  
Bill Of Materials ◽  
Porous Sio2 ◽  
Package Size ◽  
Low K ◽  
Assembly Production

To reduce the RC latency, leading edge silicon nodes employ porous SiO2 dielectrics in the interconnect stack. Introduction of porosity lowers the dielectric constant, k, but also significantly decreases both the elastic modulus and fracture toughness of the dielectric. As such, devices manufactured in silicon processes that use low K (90nm, 65nm, and 55nm) and even more so extremely low K ( 45nm, 40nm, and 28nm) interlayer dielectrics are substantially more prone to fracture as a result of package induced stresses than non porous higher K dielectrics. Since the package stresses scale with die size and package body size and inversely with bump pitch, manufacture of large die and package size flip chip devices made with extremely low K dielectrics has proven to be challenging. The stress challenge is further exacerbated by the RoHS requirements for lead free packaging which requires higher process temperatures and somewhat higher yield point solders. The combination of increased stress and reduced mechanical robustness of porous dielectrics has lead to significant reliability and assembly yield issues that have in some cases slowed the introduction of 45nm and 40nm large die lead free flip chip into the market. The work summarized in this paper shows that devices designed to withstand stresses in combination with appropriate assembly processes and bill of materials, yield highly reliable, lead free flip chip packaged devices, with die sizes greater than 400mm2 and package sizes greater than 42.5mm on a side in commercial assembly production lines.

Cu Pillar Bump FCBGA Package Design and Reliability Assessments

2008 ◽  
Author(s):  
Nicholas Kao ◽  
Yen-Chang Hu ◽  
Yuan-Lin Tseng ◽  
Eason Chen ◽  
Jeng-Yuan Lai ◽  
...  
Keyword(s):  
Stress Distribution ◽  
High Performance ◽  
Flip Chip ◽  
Spherical Geometry ◽  
Electrical Performance ◽  
Design Factor ◽  
Cu Pillar ◽  
Chip Technology ◽  
Cu Pillar Bump ◽  
Low K

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more Input/Output (I/O) and better electrical characteristics under same package form factor. Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pin accommodation and high transmission speed. However, the flip chip technology is encountering its structure limitation as the bump pitch is getting smaller and smaller because the spherical geometry bump shape is to limit the fine bump pitch arrangement and it’s also difficult to fill by underfill between narrow gaps. As this demand, a new fine bump pitch technology is developed as “Cu pillar bump” with the structure of Cu post and solder tip. The Cu pillar bump is plating process manufactured structure and composes with copper cylinder (Cu post) and mushroom shape solder cap (Solder tip). The geometry of Cu pillar bump not only provides a finer bump pitch, but also enhances the thermal performances due to the higher conductivity than conventional solder material. This paper mainly characterized the Cu pillar bump structure stress performances of FCBGA package to prevent reliability failures by finite element models. First, the bump stress and Cu/low-k stress of Cu pillar bump were studied to compare with conventional bump structure. The purpose is to investigate the potential reliability risk of Cu pillar bump structure. Secondly, the bump stress and Cu/low-k stress distribution were evaluated for different Polyimide (PI) layer, Under Bump Metallization (UBM) size and solder mask opening (SMO) size. This study can show the stress contribution of each design factor. Thirdly, a matrix which combination UBM size, Cu post thickness, SMO size, PI opening and PI thickness were studied to observe the stress distribution. Finally, the stress simulation results were experimentally validated by reliability tests.

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