scholarly journals Assembly of Cu Wirings with Ultrasmooth and High-Adhesive Electroless Cu Seed Layer by Using UV Modification and Low Attenuation of High-Frequency Transmission Property

2020 ◽  
Vol 17 (2) ◽  
pp. 45-51
Author(s):  
Masaya Toba ◽  
Shuji Nomoto ◽  
Nobuhito Komuro ◽  
Kazuyuki Mitsukura ◽  
Shinichiro Abe ◽  
...  
Keyword(s):  
Seed Layer ◽  
High Performance ◽  
Flip Chip ◽  
Printed Circuit Boards ◽  
Peel Strength ◽  
60 Ghz ◽  
Circuit Boards ◽  
Seed Formation ◽  
Anchoring Effect ◽  
Semiconductor Packages

Abstract Semiconductor packages for high-performance devices with printed circuit boards having multiwiring layers such as flip-chip ball grid array have been attracting the attention to realize ultrare-liable and low-latency communications in 5G networking. Cu wirings for the package are usually fabricated by via formation by laser for dielectric, desmear, electroless Cu seed formation, photoresist patterning, electrolytic Cu plating, resist stripping, and seed layer etching. Although a desmear process can obtain enough adhesion between dielectric and Cu seed layer by anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of a desmear process, we applied a UV modification for the surface of dielectric to realize a smooth and high-adhesive seed layer against dielectric. We obtained .8 kN/m of peel strength between dielectric and Cu seed layer in spite of surface roughness of the dielectric being 45 nm by a nanolevel anchoring effect at the UV-modified layer. Because of the smooth interface by UV modification, the S21 value of microstrip line was 26% improved compared with that assembled through the desmear process at 60 GHz.

Semi-additive Process Based Cu Wirings with Ultra Smooth Electroless Cu Seed Layer and Important Factor for High Frequency Transmission Property

2019 ◽  
Vol 2019 (1) ◽  
pp. 000409-000414
Author(s):  
Masaya Toba ◽  
Shuji Nomoto ◽  
Nobuhito Komuro ◽  
Kazuyuki Mitsukura ◽  
Shinichiro Abe ◽  
...  
Keyword(s):  
Seed Layer ◽  
High Performance ◽  
Printed Circuit Boards ◽  
Peel Strength ◽  
60 Ghz ◽  
Circuit Boards ◽  
Additive Process ◽  
Seed Formation ◽  
Anchoring Effect ◽  
Semiconductor Packages

Abstract Semiconductor packages for high performance devices with printed circuit boards having multi wiring layers such as FC-BGA have been attracting the attention in order to realize ultra-reliable and low latency communications in 5G networking. Cu wirings for the package are usually fabricated by via formation by laser for dielectric, desmear, electroless Cu seed formation, photoresist patterning, electrolytic Cu plating, resist stripping and seed layer etching. Though a desmear process can obtain enough adhesion between dielectric and Cu seed layer by anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of a desmear process, we applied an UV modification for the surface of dielectric in order to realize a smooth and high adhesive seed layer against dielectric. We obtained 0.8 kN/m of peel strength between dielectric and Cu seed layer in spite of surface roughness (Ra) of dielectric was 45 nm by nano-level anchoring effect at UV modified layer. Due to the smooth interface by UV modification, S21 value of microstrip line was 26 % improved compared to that assembled through desmear process at 60 GHz.

Electroless Plating with UV Modification for Thermosetting Dielectric and Decay Suppression of High Frequency Transmission Property

2020 ◽  
Vol 2020 (1) ◽  
pp. 000174-000180
Author(s):  
Masaya Toba ◽  
Kazuyuki Mitsukura ◽  
Masaki Yamaguchi
Keyword(s):  
Surface Roughness ◽  
Seed Layer ◽  
High Performance ◽  
Printed Circuit Boards ◽  
Peel Strength ◽  
Circuit Boards ◽  
Additive Process ◽  
Anchoring Effect ◽  
Cu Film ◽  
Semiconductor Packages

Abstract Semiconductor packages for high performance devices with printed circuit boards having multi wiring layers such as FC-BGA have been attracting the attention in order to realize ultra-reliable and low latency communications in 5G networking. Cu wirings for the package are usually fabricated by semi-additive process (SAP) with desmear process and/or modified semi-additive process (MSAP) by using Cu film with large surface roughness. Though a desmear process and Cu film can obtain enough adhesion between dielectric and Cu seed layer by anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of that processes, we applied an UV modification for the surface of our developed thermosetting dielectric in order to realize a smooth and high adhesive seed layer against the dielectric. We obtained 0.5 kN/m of peel strength between dielectric and Cu seed layer in spite of surface roughness (Ra) of dielectric was 265 nm by nano-level anchoring effect at UV modified layer. Due to the smooth interface by UV modification, the normalized S21 value of microstrip line was about 29 % improved compared to that assembled through Cu film with Ra of 2400 nm at 50 GHz.

scholarly journals Electroless Plating with UV Modification for Thermosetting Dielectric and Decay Suppression of High Frequency Transmission Property

2021 ◽  
Vol 18 (2) ◽  
pp. 51-58
Author(s):  
Masaya Toba ◽  
Kazuyuki Mitsukura ◽  
Masaki Yamaguchi
Keyword(s):  
Surface Roughness ◽  
Seed Layer ◽  
High Performance ◽  
Printed Circuit Boards ◽  
Peel Strength ◽  
Strip Line ◽  
Additive Process ◽  
Anchoring Effect ◽  
Cu Film ◽  
Semiconductor Packages

Abstract Semiconductor packages for high-performance devices with printed circuit boards having multi-wiring layers such as FC-BGA have been attracting attention to realize ultrareliable and low-latency communications in 5G networking. Cu wirings for the package are usually fabricated by the semi-additive process (SAP) with the de-smear process and/or the modified semi-additive process (MSAP) by using Cu film with large surface roughness. Although a de-smear process and Cu film can obtain enough adhesion between dielectric and Cu seed layer by the anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of those processes, we applied UV modification for the surface of our developed thermosetting dielectric to realize a smooth and high-adhesive seed layer against the dielectric. We obtained .5 kN/m of peel strength between dielectric and Cu seed layer despite surface roughness (Ra) of dielectric being 265 nm by the nano-level anchoring effect at UV modified layer. Because of the smooth interface by UV modification, the normalized S21 value of micro-strip line was about 29% improved compared with that assembled through Cu film with Ra of 2,400 nm at 50 GHz.

High Temperature Laminate Characterization

2014 ◽  
Vol 2014 (HITEC) ◽  
pp. 000235-000245
Author(s):  
David Shaddock ◽  
Liang Yin
Keyword(s):  
Weight Loss ◽  
High Temperature ◽  
Printed Circuit Boards ◽  
Stress Test ◽  
Model Development ◽  
Peel Strength ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Mean Lifetime ◽  
The Mean

Printed circuit boards have been reported to have limited lifetime at 200 to 250°C. Characterization and modeling high temperature laminates for application at 200 to 250°C was conducted to better quantify the mean lifetime using accelerated testing of key functional parameters. Life testing and model development was applied for via cyclic life, peel strength, and weight loss. Four high temperature laminates consisting of 2 types were evaluated. Via lifetime was characterization using Interconnect Stress Test (IST) coupons. Peel strength was tested using IPC IPC-TM-650 method 2.4.8c. Weight loss was characterized using isothermal aging. Comparison of lifetime is made between the laminate samples.

Investigation of Micro-Drilling for Printed Circuit Boards Containing High-Hardness Fillers

2012 ◽  
Vol 565 ◽  
pp. 442-447 ◽  
Author(s):  
Taiji Funabiki ◽  
Toshiki Hirogaki ◽  
Eiichi Aoyama ◽  
Keiji Ogawa ◽  
Hiroyuki Kodama
Keyword(s):  
Thermal Conductivity ◽  
Cutting Force ◽  
High Performance ◽  
Printed Circuit Boards ◽  
High Hardness ◽  
High Thermal Conductivity ◽  
Digital Cameras ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Micro Drilling

This paper describes micro-drilling processes for printed circuit boards (PCBs) containing fillers with high hardness and high thermal conductivity. Inspired primarily by devices such as digital cameras, laptop computers, and wireless communications devices, the electronics field today is continuously demanding smaller, lighter, and more technologically advanced high performance devices. However, that the increase in semiconductor-generated heat tends to affect such devices negatively. Additionally, from the viewpoint of environmental problems, electric vehicles and LEDs are being developed actively. PCBs are one of the principal components for building such devices. In recent years, PCBs containing alumina fillers with high thermal conductivity have been developed and begun to be widely used. However, when processing these PCBs, the drill tools become severely worn because of the filler’s high hardness. We therefore examined the drill wear characteristics. The results show the filler is the main factor that causes drill wear, while the increase in cutting force does not affect it. The cutting force increases with the drill wear linearly. Moreover, the characteristic of PCBs with higher filler content rates is close to that of inorganic material like ceramics.

Thick Film Resistor Failures

2008 ◽  
Author(s):  
Anshul Shrivastava ◽  
Ahmed Amin ◽  
Bhanu Sood ◽  
Michael Azarian ◽  
Michael Pecht ◽  
...  
Keyword(s):  
Thick Film ◽  
High Performance ◽  
Printed Circuit Boards ◽  
Failure Modes ◽  
Environmental Scanning Electron Microscopy ◽  
Environmental Scanning ◽  
Physical Analysis ◽  
Circuit Boards ◽  
Molding Compound ◽  
Electron Microscopy Analysis

Abstract Thick film resistors are widely used in consumer and industrial products such as timers, motor controls and a broad range of high performance electronic equipment. This article provides information on failures due to copper dendrite growth, silver migration, sulfur atmosphere corrosion, variation of temperature, and crack due to molding compound mechanisms. It presents case studies in which a physical analysis plan was developed and executed to investigate these sites of interest on as-manufactured and failed thick film power resistors. The analysis techniques included X-ray inspection, cross-sectioning, decapsulation, and optical and environmental scanning electron microscopy analysis. A table illustrates different failure modes and mechanisms for thick film resistors, and also potential application and manufacturing factors that cause failure mechanisms, which then describe the failure modes. The article is concluded that by preventing the failure of thick film resistors, printed circuit boards can be kept in service for their full lifetime.

scholarly journals Process to Improve the Adherences of Copper to a PTFE Plate

2016 ◽  
Vol 2016 ◽  
pp. 1-4
Author(s):  
Abel Pérez ◽  
Alfonso Torres ◽  
Reydezel Torres
Keyword(s):  
High Frequency ◽  
Printed Circuit Boards ◽  
Low Pressure ◽  
Peel Strength ◽  
Plasma Power ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Free Process

A simple low plasma power and roughness free process for improving the adherence of Cu to PTFE is presented. The results show that low pressure and Ar flow combination are the drivers of this improved adherence. Copper Peel Strength Tensile values up to 60 kg/m are obtained which are comparable to those shown in commercial composite dielectrics for high-frequency applications Printed Circuit Boards.

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