The Chip Scale Package

Sample Preparation Challenges In WLCSP Epoxy Underfill Coating Removal

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0471 ◽

2012 ◽

Author(s):

Jason H. Lagar ◽

Rudolf A. Sia

Keyword(s):

Sample Preparation ◽

Failure Analysis ◽

Vital Role ◽

Fault Isolation ◽

Wafer Level ◽

Chip Scale Package ◽

Coating Removal ◽

Customer Returns ◽

Preparation Techniques ◽

Mechanical Defect

Abstract Most Wafer Level Chip Scale Package (WLCSP) units returned by customers for failure analysis are mounted on PCB modules with an epoxy underfill coating. The biggest challenge in failure analysis is the sample preparation to remove the WLCSP device from the PCB without inducing any mechanical defect. This includes the removal of the underfill material to enable further electrical verification and fault isolation analysis. This paper discusses the evaluations conducted in establishing the WLCSP demounting process and removal of the epoxy underfill coating. Combinations of different sample preparation techniques and physical failure analysis steps were evaluated. The established process enabled the electrical verification, fault isolation and further destructive analysis of WLCSP customer returns mounted on PCB and with an epoxy underfill coating material. This paper will also showcase some actual full failure analysis of WLCSP customer returns where the established process played a vital role in finding the failure mechanism.

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Ultra Thin Hermetic Wafer level, Chip Scale Package

56th Electronic Components and Technology Conference 2006 ◽

10.1109/ectc.2006.1645794 ◽

2006 ◽

Cited By ~ 5

Author(s):

L. Shiv ◽

M. Heschel ◽

H. Korth ◽

S. Weichel ◽

R. Hauffe ◽

...

Keyword(s):

Wafer Level ◽

Chip Scale Package

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Mechanical strength of chip scale package with various underfills under accelerated thermal condition

Materials Science and Technology ◽

10.1179/174328407x192750 ◽

2007 ◽

Vol 23 (7) ◽

pp. 828-832 ◽

Cited By ~ 1

Author(s):

B.-I. Noh ◽

B.-Y. Lee ◽

S.-B. Jung

Keyword(s):

Mechanical Strength ◽

Thermal Condition ◽

Chip Scale Package

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Influence of compliant layer thickness on stress and strain of solder joints in wafer level chip scale package under thermal cycle

2014 15th International Conference on Electronic Packaging Technology ◽

10.1109/icept.2014.6922722 ◽

2014 ◽

Cited By ~ 1

Author(s):

Liang Ying ◽

Huang Chunyue ◽

Zhang Xin ◽

Li Tianming ◽

Guo Guangkuo ◽

...

Keyword(s):

Layer Thickness ◽

Thermal Cycle ◽

Solder Joints ◽

Stress And Strain ◽

Wafer Level ◽

Chip Scale Package ◽

Compliant Layer

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Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications

Journal of Electronic Packaging ◽

10.1115/1.1462626 ◽

2002 ◽

Vol 124 (3) ◽

pp. 205-211 ◽

Cited By ~ 12

Author(s):

John H. Lau ◽

S. W. Ricky Lee ◽

Stephen H. Pan ◽

Chris Chang

Keyword(s):

Cross Sections ◽

Flip Chip ◽

Printed Circuit Board ◽

Low Cost ◽

Circuit Board ◽

Test Results ◽

Pcb Assembly ◽

Creep Analysis ◽

Chip Scale Package ◽

Time Dependent Analysis

An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the thermal cycling test results of the micro VIP CSP PCB assembly is presented.

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