Low-Power Processor Array Design Strategy for Solving Computationally Intensive 2D Topographic Problems

2009 ◽  
pp. 215-245
Author(s):  
Ákos Zarándy ◽  
Csaba Rekeczky
Keyword(s):  
Low Power ◽  
Design Strategy ◽  
Processor Array ◽  
Array Design ◽  
Computationally Intensive

Low-power RRAM Device based 1T1R Array Design with CNTFET as Access Device

2019 ◽  
Author(s):  
Furqan Zahoor ◽  
Tun Zainal Azni Zulkifli ◽  
Farooq Ahmad Khanday ◽  
Aabid Amin Fida
Keyword(s):  
Low Power ◽  
Array Design ◽  
Access Device

MuCCRA-3: A low power dynamically Reconfigurable Processor Array

2010 ◽  
Author(s):  
Yoshiki Saito ◽  
Toru Sano ◽  
Masaru Kato ◽  
Vasutan Tunbunheng ◽  
Yoshihiro Yasuda ◽  
...  
Keyword(s):  
Low Power ◽  
Processor Array ◽  
Reconfigurable Processor ◽  
Dynamically Reconfigurable

Research of Low Power Design Strategy Based on IEEE 1801 Unified Power Format

2014 ◽  
Vol 981 ◽  
pp. 21-24
Author(s):  
Shu Ping Cui ◽  
Chuang Xie
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
High Power ◽  
Low Power Design ◽  
Design Strategy ◽  
Design Flow ◽  
Battery Life ◽  
Electronic Systems ◽  
High Power Consumption

Power consumption is becoming an increasingly important aspect of circuit design. High power consumption can lead to high machine temperature, short battery life which makes laptop electronics difficult to be widely used. IEEE 1801 Unified Power Format (UPF) is designed to express power intent for electronic systems and components .This paper first introduces the power principles, puts forward the approaches to reduce power consumption according to UPF, and then demonstrates the Synopsys design flow based on UPF, finally gives the power report and makes a conclusion.

Low-Cost Subarrayed Sensor Array Design Strategy for IoT and Future 6G Applications

2020 ◽  
Vol 7 (6) ◽  
pp. 4816-4826
Author(s):  
Wei Dong ◽  
Zhen-Hai Xu ◽  
Xin-Xin Li ◽  
Shun-Ping Xiao
Keyword(s):  
Sensor Array ◽  
Low Cost ◽  
Design Strategy ◽  
Array Design

Memristor-Based Low-Power High-Speed Nonvolatile Hybrid Memory Array Design

2017 ◽  
Vol 36 (9) ◽  
pp. 3585-3597 ◽  
Author(s):  
Khandoker Asif Faruque ◽  
Baishakhi Rani Biswas ◽  
A. B. M. Harun-ur Rashid
Keyword(s):  
Low Power ◽  
High Speed ◽  
Array Design ◽  
Memory Array ◽  
Hybrid Memory
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