Memristor-Based Low-Power High-Speed Nonvolatile Hybrid Memory Array Design

2017 ◽  
Vol 36 (9) ◽  
pp. 3585-3597 ◽  
Author(s):  
Khandoker Asif Faruque ◽  
Baishakhi Rani Biswas ◽  
A. B. M. Harun-ur Rashid
Keyword(s):  
Low Power ◽  
High Speed ◽  
Array Design ◽  
Memory Array ◽  
Hybrid Memory

scholarly journals Strategic Development of Low Power High Speed SRAM Array Design

2019 ◽  
Vol 8 (6) ◽  
pp. 4280-4285
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Error Correction ◽  
Main Parameter ◽  
High Speed ◽  
Strategic Development ◽  
Array Design ◽  
Power Cell ◽  
Technology Nodes ◽  
Memory Layout

Because of the system variations of tiny functional size, enhanced adjustment functions in bits are becoming more and more vital, as technology nodes proceed to scale, primary memory encounter increased energy with output and time impacts such as crosstalk, challenges in consumption and reliability. We suggest a sustainable strategy to error correction in deeply-scale memories in order to tackle increasing failure rates owing to issues. SRAM is frequently used for high-speed memory apps like cache. The SRAM memory layout (SRAM) main parameter is power consumption. SRAM cells are power starving and bad in traditional models. The low-power cell designs for power consumption, delay write and the power retard product has been analyzed in this paper. The most recent upgrade VLSI, primarily in the volatile memory form of the SRAM set built into the PMOS & NMOS series and which is to be included in the cache segment on the CPU and in microcontrollers that are electronically energy-related, and now we have improved the SRAM Array challenges

scholarly journals 7T Based SRAM Topologies with Low Power and Higher SNM

2019 ◽  
Vol 8 (11) ◽  
pp. 2779-2783
Keyword(s):  
Low Power ◽  
Significant Role ◽  
Portable Devices ◽  
Power Requirement ◽  
Array Design ◽  
Memory Array ◽  
Higher Power ◽  
Better Than ◽  
Standard Library

Now the era is of electronic gadgets like processors and portable devices, in which Memory plays a significant role through the usage of Static RAMs (SRAMs).Hence designing of Low power SRAM is immense for applications. But the design of SRAM is involved in higher power requirement. So there is still scope for adequate Low power Memory Array design. The Main Moto of this paper is involved in designing & Simulating Low Power 16x16 SRAM Arrays using 7T SRAM cells based on Conventional, Self Controllable Voltage (SVL) & Improved Self Controllable Voltage (I-SVL) methods. Also Comparative Power and SNM Analysis is carried between Conventional 7T, 7T-SVL and 7T-ISVL based Arrays. The Proposed Array using 7T Cell consumes 6.24mW which is 67.64% lesser than the Array design [2].Also I-SVL based 7T SNM is better than the SVL-7T and 7T based cell.The proposed work is carried using cadence virtuoso tool with standard library gpdk 180nm.Also Proposed Array based on I-SVL is efficient in terms of power. The proposed Cell SNM resulted in 68.57% higher in comparison with existing cell of 8T and 10T [3]

HIGH SPEED AND LOW POWER 4*4 ARRAY MULTIPLIER DESIGN

2019 ◽  
Vol 7 (1) ◽  
pp. 24
Author(s):  
N. SURESH ◽  
K. S. SHAJI ◽  
KISHORE REDDY M. CHAITANYA ◽  
◽  
◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Array Multiplier

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

Low-temperature f.e.t. for low-power high-speed logic

1977 ◽  
Vol 13 (6) ◽  
pp. 156 ◽  
Author(s):  
H. Rees ◽  
G.S. Sanghera ◽  
R.A. Warriner
Keyword(s):  
Low Temperature ◽  
Low Power ◽  
High Speed
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