Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores

2002 ◽  
pp. 165-174
Author(s):  
Chen Li ◽  
Xiaoliang Bai ◽  
Sujit Dey ◽  
Krishnendu Chakrabarty
Keyword(s):  
Embedded Processor ◽  
On Chip ◽  
Processor Cores

Performance Analysis of FPGA Architectures based Embedded Control Applications

2011 ◽  
pp. 274-310 ◽  
Author(s):  
Slim Ben Othman ◽  
Ahmed Karim Ben Salem ◽  
Slim Ben Saoud
Keyword(s):  
Electrical Machine ◽  
Embedded Processor ◽  
Embedded Control ◽  
Digital Devices ◽  
Field Programmable ◽  
Speed Performance ◽  
Fpga Chip ◽  
On Chip ◽  
Machine Drives ◽  
Processor Cores

The performances of System on Chip (SoC) and the Field Programmable Gate Array (FPGA) particularly, are increasing continually. Due to the growing complexity of modern embedded control systems, the need of more performance digital devices is evident. Recent FPGA technology makes it possible to include processor cores into the FPGA chip, which ensures more flexibility for digital controllers. Indeed, greater functionality of hardware and system software, Real-Time (RT) platforms and distributed subsystems are demanded. In this chapter, a design concept of FPGA based controller with Hardware/Software (Hw/Sw) codesign is proposed. It is applied for electrical machine drives. There are discussed different MultiProcessor SoC (MPSoC) architectures with Hw peripherals for the implementation on FPGA-based embedded processor cores. Hw accelerators are considered in the design to enhance the controller speed performance and reduce power consumption. Test and validation of this control system are performed on a RT motor emulator implemented on the same FPGA. Experimental results, carried on a real prototyping platform, are given in order to analyze the performance and efficiency of discussed architecture designs helping to support hard RT constraints.

Flexible Implementation of Industrial Real-Time Servo Drive System

2011 ◽  
pp. 476-508 ◽  
Author(s):  
Ahmed Karim Ben Salem ◽  
Hedi Abdelkrim ◽  
Slim Ben Saoud
Keyword(s):  
Real Time ◽  
Servo Drive ◽  
Embedded Processor ◽  
Field Programmable ◽  
Flexible Architecture ◽  
Function Blocks ◽  
On Chip ◽  
Intellectual Properties ◽  
Servo Drive System ◽  
Processor Cores

The research presented in this chapter deals with the design and implementation of Real-Time (RT) control systems applying advanced Field Programmable Gate Array (FPGAs). The chapter proposes a promising flexible architecture that uses RT Operating System (RTOS) and ready-to-use Intellectual Properties (IPs). The authors detail an approach that uses software closed control loop function blocks (FB), running on embedded processor cores. These FBs implement the different control drive sub-modules into RTOS tasks of the execution environment, where each task has to be executed under well defined conditions. Two RTOSes are evaluated: µC-OS/II and Xilkernel. The FPGA embedded processor cores are combined with reconfigurable logic and dedicated resources on the FPGA. This System-on-Chip (SoC) has been applied to electric motors drive. A comparative analysis, in terms of speed and cost, is carried-out between various hardware/software FPGA-based architectures, in order to enhance flexibility without sacrificing performance and increasing cost. Case studies results validate successfully the feasibility and the efficiency of the flexible approach for new and more complex control algorithms. The performance and flexibility of FPGA-based motor controllers are enhanced with the reliability and modularity of the introduced RTOS support.

Advanced Technologies for Transient Faults Detection and Compensation

2011 ◽  
pp. 132-154
Author(s):  
Matteo Sonza Reorda ◽  
Luca Sterpone ◽  
Massimo Violante
Keyword(s):  
Market Failure ◽  
Propagation Mechanism ◽  
Transient Faults ◽  
Niche Markets ◽  
Time Redundancy ◽  
Ip Cores ◽  
On Chip ◽  
Manufacturing Technologies ◽  
Processor Cores ◽  
Nuclear Applications

Transient faults became an increasing issue in the past few years as smaller geometries of newer, highly miniaturized, silicon manufacturing technologies brought to the mass-market failure mechanisms traditionally bound to niche markets as electronic equipments for avionic, space or nuclear applications. This chapter presents the origin of transient faults, it discusses the propagation mechanism, it outlines models devised to represent them and finally it discusses the state-of-the-art design techniques that can be used to detect and correct transient faults. The concepts of hardware, data and time redundancy are presented, and their implementations to cope with transient faults affecting storage elements, combinational logic and IP-cores (e.g., processor cores) typically found in a System-on-Chip are discussed.

scholarly journals Low-Power Pedestrian Detection System on FPGA

Proceedings ◽  
2019 ◽  
Vol 31 (1) ◽  
pp. 35 ◽  
Author(s):  
Vinh Ngo ◽  
David Castells-Rufas ◽  
Arnau Casadevall ◽  
Marc Codina ◽  
Jordi Carrabina
Keyword(s):  
Low Power ◽  
Detection System ◽  
Low Cost ◽  
Pedestrian Detection ◽  
Support Vector ◽  
Embedded Processor ◽  
Car Industry ◽  
Field Programmable ◽  
On Chip ◽  
Histogram Of Gradients

Pedestrian detection is one of the key problems in the emerging self-driving car industry. In addition, the Histogram of Gradients (HOG) algorithm proved to provide good accuracy for pedestrian detection. Many research works focused on accelerating HOG algorithm on FPGA (Field-Programmable Gate Array) due to its low-power and high-throughput characteristics. In this paper, we present an energy-efficient HOG-based implementation for pedestrian detection system on a low-cost FPGA system-on-chip platform. The hardware accelerator implements the HOG computation and the Support Vector Machine classifier, the rest of the algorithm is mapped to software in the embedded processor. The hardware runs at 50 Mhz (lower frequency than previous works), thus achieving the best pixels processed per clock and the lower power design.

scholarly journals Run Control Software For The Upgrade Of The Atlas Muon To Central Trigger Processor Interface (MUCTPI)

2019 ◽  
Vol 214 ◽  
pp. 01034
Author(s):  
Ralf Spiwoks ◽  
Aaron Armbruster ◽  
German Carrillo-Montoya ◽  
Magda Chelstowska ◽  
Patrick Czodrowski ◽  
...  
Keyword(s):  
Hadron Collider ◽  
Programmable Logic ◽  
Trigger System ◽  
Control Software ◽  
Atlas Experiment ◽  
Arm Processor ◽  
Level 1 ◽  
On Chip ◽  
Control Application ◽  
Processor Cores

The Muon to Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron Collider(LHC) at CERN is being upgraded for the next run of the LHC in order to use optical inputs and to provide full-precision information for muon candidates to the topological trigger processor (L1TOPO) of the Level-1 trigger system. The new MUCTPI is implemented as a single ATCA blade with high-end processing FPGAs which eliminate doublecounting of muon candidates in overlapping regions, send muon candidates to L1TOPO, and muon multiplicities tothe Central Trigger Processor (CTP), as well as readout data to the data acquisition system of the experiment. A Xilinx Zynq System-on-Chip (SoC) with a programmable logic part and a processor part is used for the communication to the processing FPGAs and the run control system. The processor part, based on ARM processor cores, is running embedded Linux prepared using the framework of the Linux Foundation's Yocto project. The ATLAS run control software was ported to the processor part and a run control application was developed which receives, at configuration, all data necessary for the overlap handling and candidate counting of the processing FPGAs. During running, the application provides ample monitoring of the physics data and of the operation of the hardware. *

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