Physics of Heterostructures and Heterostructure Devices

1988 ◽  
pp. 445-475
Author(s):  
Peter J. Price
Keyword(s):  
Heterostructure Devices

Hybrid inorganic-organic light-emitting heterostructure devices based on ZnO

2021 ◽  
Vol 138 ◽  
pp. 106896
Author(s):  
Mahdiyar Nouri Rezaie ◽  
Shahram Mohammadnejad ◽  
Shabnam Ahadzadeh
Keyword(s):  
Light Emitting ◽  
Organic Light ◽  
Heterostructure Devices

Current Rectification, Resistive Switching, and Stable NDR Effect in BaTiO 3 /CeO 2 Heterostructure Devices

2021 ◽  
pp. 2001237
Author(s):  
Shania Rehman ◽  
Honggyun Kim ◽  
Harshada Patil ◽  
Kalyani D. Kadam ◽  
Rizwan Ur Rehman Sagar ◽  
...  
Keyword(s):  
Resistive Switching ◽  
Current Rectification ◽  
Heterostructure Devices

Current‐controlled negative differential resistance in four‐terminal heterostructure devices

1989 ◽  
Vol 54 (24) ◽  
pp. 2452-2454 ◽  
Author(s):  
A. Kastalsky ◽  
M. Milshtein ◽  
L. G. Shantharama ◽  
J. Harbison ◽  
L. Florez
Keyword(s):  
Negative Differential Resistance ◽  
Differential Resistance ◽  
Heterostructure Devices

Heterostructure devices: A device physicist looks at interfaces

1983 ◽  
Vol 132 (1-3) ◽  
pp. 543-576 ◽  
Author(s):  
Herbert Kroemer
Keyword(s):  
Heterostructure Devices

scholarly journals Current–voltage characteristics of organic heterostructure devices with insulating spacer layers

2015 ◽  
Vol 24 ◽  
pp. 26-29 ◽  
Author(s):  
Sun Yin ◽  
Wanyi Nie ◽  
Aditya D. Mohite ◽  
Avadh Saxena ◽  
Darryl L. Smith ◽  
...  
Keyword(s):  
Current Voltage ◽  
Current Voltage Characteristics ◽  
Heterostructure Devices

scholarly journals SAT-Attack Resistant Hardware Obfuscation using Camouflaged Two-Dimensional Heterostructure Devices

2020 ◽  
Author(s):  
Akshay Wali ◽  
Andrew Arnold ◽  
Shamik Kundu ◽  
Soumyadeep Choudhury ◽  
Kanad Basu ◽  
...  
Keyword(s):  
Transition Metal ◽  
Reverse Engineering ◽  
Field Effect Transistors ◽  
Semiconductor Industry ◽  
Logic Gates ◽  
Pattern Generation ◽  
Oxide Semiconductor ◽  
Two Dimensional ◽  
Area Overhead ◽  
Heterostructure Devices

Abstract Reverse engineering (RE) is one of the major security threats to the semiconductor industry due to the involvement of untrustworthy parties in an increasingly globalized chip manufacturing supply chain [1-5]. RE efforts have already been successful in extracting device level functionalities from an integrated circuit (IC) with very limited resources [6]. Camouflaging is an obfuscation method that can thwart such RE [7-9]. Existing work on IC camouflaging primarily uses fabrication techniques such as doping and dummy contacts to hide the circuit structure or build cells that look alike but have different functionalities. While promising these Si complementary metal oxide semiconductor (CMOS) based obfuscation techniques adds significant area overhead and are successfully decamouflaged by the Satisfiability solver (SAT)-based reverse engineering techniques [9-13]. Emerging solutions, such as polymorphic gates based on giant spin Hall effect (GSHE) are promising but adds delay overhead in hybrid CMOS-GSHE designs restricting the camouflaging to a maximum of 15% of all the gates in the circuit. Here, we harness the unique properties of two-dimensional (2D) transition metal dichalcogenides (TMDs) including MoS2, MoSe2, MoTe2, WS2, and WSe2 and their optically transparent transition metal oxides (TMOs) to demonstrate novel area efficient camouflaging solutions that are resilient to SAT-attack and automatic test pattern generation (ATPG) attacks. We show that resistors with resistance values differing by 8 orders of magnitude, diodes with variable turn-on voltages and reverse saturation currents, and field effect transistors (FETs) with adjustable conduction type, threshold voltages and switching characteristics can be optically camouflaged to look exactly similar by engineering TMO/TMD heterostructures allowing hardware obfuscation of both digital and analog circuits. Since this 2D heterostructure devices family is intrinsically camouflaged, NAND/NOR/AND/OR gates in the circuit can be obfuscated with significantly less area overhead allowing 100% logic obfuscation compared to only 5% for CMOS-based camouflaging. Finally, we demonstrate that the largest benchmarking circuit from ISCAS’85, comprised of more than 4000 logic gates when obfuscated with the CMOS-based technique are successfully decamouflaged by SAT-attack in less than 40 minutes; whereas, it renders to be invulnerable even in more than 10 hours, when camouflaged with 2D heterostructure devices thereby corroborating our hypothesis of high resilience against RE. Our approach of connecting unique material properties to innovative devices to secure circuits can be considered as one of its kind demonstrations, highlighting the benefits of cross-layer optimization.

Metal/molecule/p-type GaAs heterostructure devices

2006 ◽  
Vol 100 (2) ◽  
pp. 024503 ◽  
Author(s):  
Saurabh Lodha ◽  
David B. Janes
Keyword(s):  
P Type ◽  
Heterostructure Devices

Influence of the interface structure and strain on the rectification performance of lateral MoS2/graphene heterostructure devices

2022 ◽  
Author(s):  
Shun Song ◽  
Jian Gong ◽  
Xiangwei Jiang ◽  
Shenyuan Yang
Keyword(s):  
Transport Properties ◽  
Quantum Transport ◽  
First Principles ◽  
Interface Structure ◽  
First Principles Calculations ◽  
Heterostructure Devices

We systematically study the influence of interface configuration and strain on the electronic and transport properties of lateral MoS2/graphene heterostructures by first-principles calculations and quantum transport simulations.

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