scholarly journals Online Test Strategies and Optimizations for Reliable Reconfigurable Architectures

2020 ◽  
pp. 277-302
Author(s):  
Lars Bauer ◽  
Hongyan Zhang ◽  
Michael A. Kochte ◽  
Eric Schneider ◽  
Hans-Joachim Wunderlich ◽  
...  
Keyword(s):  
Design Method ◽  
High Reliability ◽  
Test Methods ◽  
Reconfigurable Architectures ◽  
Central Processing ◽  
Online Test ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Reconfigurable Fabric ◽  
Online Tests

AbstractRuntime/reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are a promising augment to conventional processor architectures such as Central Processing Units (CPUs) and Graphic Processing Units (GPUs). Since the reconfigurable parts are typically manufactured in the latest technology, they may suffer from aging and environmentally induced dependability threats. In this chapter, strategic online test methods for dependable runtime-reconfigurable architectures as well as cross-layer optimizations for high reliability and lifetime are developed. Firstly, two orthogonal online tests are proposed that ensure reliable configuration of the reconfigurable fabric and aid fault detection. Secondly, a novel design method called module diversification is presented that enables self-repair of the system in case of faults caused by degradation effects as well as single-event upsets in the configuration. Thirdly, a novel stress-aware placement method is proposed that aims for slowing down system degradation by aging effects. The combined methods ensure reliable operation across architectural and gate level and allow to prolong the lifetime of dependable runtime-reconfigurable architectures.

scholarly journals Real-Time Monte Carlo Optimization on FPGA for the Efficient and Reliable Message Chain Structure

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 866 ◽  
Author(s):  
Heoncheol Lee ◽  
Kipyo Kim
Keyword(s):  
Monte Carlo ◽  
Real Time ◽  
Communication Systems ◽  
Optimization Method ◽  
Chain Structure ◽  
Processing Unit ◽  
Monte Carlo Optimization ◽  
Central Processing ◽  
Field Programmable ◽  
Programmable Gate Arrays

This paper addresses the real-time optimization problem to find the most efficient and reliable message chain structure in data communications based on half-duplex command–response protocols such as MIL-STD-1553B communication systems. This paper proposes a real-time Monte Carlo optimization method implemented on field programmable gate arrays (FPGA) which can not only be conducted very quickly but also avoid the conflicts with other tasks on a central processing unit (CPU). Evaluation results showed that the proposed method can consistently find the optimal message chain structure within a quite small and deterministic time, which was much faster than the conventional Monte Carlo optimization method on a CPU.

scholarly journals Benchmarking Analysis of Space-Grade Central Processing Units and Field-Programmable Gate Arrays

2018 ◽  
Vol 15 (8) ◽  
pp. 518-529 ◽  
Author(s):  
Tyler M. Lovelly ◽  
Travis W. Wise ◽  
Shaun H. Holtzman ◽  
Alan D. George
Keyword(s):  
Field Programmable Gate Arrays ◽  
Central Processing ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

Development of FPGA-Based Safety-Related I&C Systems

2004 ◽  
Author(s):  
Naotaka Oda ◽  
Teruji Tarumi ◽  
Atsushi Tanaka ◽  
Mikio Izumi ◽  
Toshifumi Sato
Keyword(s):  
Analog Circuits ◽  
Digital Circuit ◽  
The Other ◽  
Development Method ◽  
Central Processing ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Long Life ◽  
Conventional Systems

Toshiba has developed FPGA-based systems which perform signal processing by field programmable gate arrays (FPGA) for safety-related I&C systems. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing units (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. Considering application to safety-related systems, nonvolatile and non rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. The systems which Toshiba developed this time are Power range Monitor (PRM) and Trip Module (TM). These systems are compatible with the conventional analog-based systems and the CPU-based systems. Therefore, requested cost for upgrading will be minimized. Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on.

Flow Measurement with Digital Correlator Realized by FPGA

2012 ◽  
Vol 462 ◽  
pp. 641-646
Author(s):  
Yan Long Wang ◽  
Jun Hua Zhang ◽  
Lu Lu Bu ◽  
Jun Yang ◽  
Xin Ling Shi
Keyword(s):  
Measurement System ◽  
Flow Measurement ◽  
Cross Correlation ◽  
High Reliability ◽  
Gate Arrays ◽  
Time Flow ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
The Cross ◽  
Digital Correlator

Cross correlator is the core device of the cross-correlation flow measurement system. This paper describes the theory of the cross-correlation flow measurement system and realizes the digital correlator for flow measurement based on field programmable gate arrays (FPGA). The correlation algorithm is realized by verilog language, and the result of Modelsim simulation shows that this correlator can be used to calculate the cross functions of random signal. This correlator which has a simple hardware structure, high reliability and high accuracy, can meet the demand of the real-time flow measurement system.

scholarly journals Design of microprogrammed controllers to be implemented in FPGAs

2011 ◽  
Vol 21 (2) ◽  
pp. 401-412 ◽  
Author(s):  
Remigiusz Wiśniewski ◽  
Alexander Barkalov ◽  
Larisa Titarenko ◽  
Wolfgang Halang
Keyword(s):  
Design Method ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Traditional Structure ◽  
Field Programmable ◽  
Programmable Gate Arrays

Design of microprogrammed controllers to be implemented in FPGAs In the article we propose a new design method for microprogrammed controllers. The traditional structure is improved by modifying internal modules and connections. Such a solution allows reducing the total number of logic elements needed for implementation in programmable structures, especially Field Programmable Gate Arrays (FPGAs). Detailed results of experiments show that on the average the application of the proposed methods yields up to 30% savings as far as the destination device is considered.

scholarly journals FPGA Technology and Sequential Finite State Machine Method

2018 ◽  
Vol 127 (1D) ◽  
pp. 55
Author(s):  
Nguyen Khanh Quang ◽  
Nguyen Ho Quang
Keyword(s):  
Finite State Machine ◽  
Design Method ◽  
State Machine ◽  
Machine Method ◽  
Gate Arrays ◽  
Design Engineers ◽  
Finite State ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Basic Level

<em>The implementation of complex control algorithms on an FPGA</em> (Field programmable gate arrays)<em> is still at a basic level. There is no fixed method to develop algorithms on these devices because of their general characteristics. Therefore, the design engineers are still on the way to find the good approaches to optimize the implementation of algorithms on FPGAs [1-7]. This paper presents and demonstrates a sequential finite state machine design method that can solve the issue of optimal usage of the limited resources on an FPGA.</em>

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