A Low Area Probing Detector for Power Efficient Security ICs

2014 ◽  
pp. 185-197 ◽  
Author(s):  
Michael Weiner ◽  
Salvador Manich ◽  
Georg Sigl
Keyword(s):  
Power Efficient ◽  
Low Area

Low Area and High Bit Resolution Flash Analog to Digital Converter for Wide Band Applications: A Review

2021 ◽  
Vol 13 ◽  
Author(s):  
Banoth Krishna ◽  
Sandeep Singh Gill ◽  
Amod Kumar
Keyword(s):  
High Speed ◽  
Wide Band ◽  
Low Noise ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Digital To Analog Converter ◽  
Flash Adc ◽  
Analog To Digital ◽  
Power Efficient ◽  
Low Area

: This work reviews the design challenges of CMOS flash type analog-to-digital converter (ADC) for making high bit resolution, low area, low noise, low offset, and power-efficient architecture. Low-bit resolution flash ADC architecture, high-speed applications, and wide-area parallel comparators are identified on their suitability of the design for ADCs. These are effective in the area and bit resolution. The overview includes bit resolution, area, power dissipation, bandwidth and offset noise consideration for high-speed flash ADC design. A MUX-based two-step half flash architecture is considered for applications requiring 1 GHz 16-bit resolution low area and low power consumption. An advanced comparator, MUX, a high-speed digital-to-analog converter(DAC), and MUX-based encoder are also reviewed. The design of technology-efficient ADC architecture is highly challenging for the analog designer.

scholarly journals Design of Power-Efficient Training Accelerator for Convolution Neural Networks

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 787
Author(s):  
JiUn Hong ◽  
Saad Arslan ◽  
TaeGeon Lee ◽  
HyungWon Kim
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Energy Consumption ◽  
Low Power ◽  
Resource Sharing ◽  
Graphics Processing Unit ◽  
Processing Unit ◽  
Real Time Processing ◽  
Power Efficient ◽  
Low Area

To realize deep learning techniques, a type of deep neural network (DNN) called a convolutional neural networks (CNN) is among the most widely used models aimed at image recognition applications. However, there is growing demand for light-weight and low-power neural network accelerators, not only for inference but also for training process. In this paper, we propose a training accelerator that provides low power and compact chip size targeted for mobile and edge computing applications. It accelerates to achieve the real-time processing of both inference and training using concurrent floating-point data paths. The proposed accelerator can be externally controlled and employs resource sharing and an integrated convolution-pooling block to achieve low area and low energy consumption. We implemented the proposed training accelerator in an FPGA (Field Programmable Gate Array) and evaluated its training performance using an MNIST CNN example in comparison with a PC with GPU (Graphics Processing Unit). While both methods achieved a similar training accuracy of 95.1%, the proposed accelerator, when implemented in a silicon chip, reduced the energy consumption by 480 times compared to the counterpart. Additionally, when implemented on an FPGA, an energy reduction of over 4.5 times was achieved compared to the existing FPGA training accelerator for the MNIST dataset. Therefore, the proposed accelerator is more suitable for deployment in mobile/edge nodes compared to the existing software and hardware accelerators.

A POWER EFFICIENT NMOS BASED FULL ADDER USING PTL LOGIC

2017 ◽  
Vol 5 (4) ◽  
pp. 15
Author(s):  
ISWARIYA S. ◽  
RAJA M. VILASINI ◽  
◽  
Keyword(s):  
Full Adder ◽  
Power Efficient
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