Low-Leakage Secure Search for Boolean Expressions

2017 ◽  
pp. 397-413 ◽  
Author(s):  
Fernando Krell ◽  
Gabriela Ciocarlie ◽  
Ashish Gehani ◽  
Mariana Raykova
Keyword(s):  
Low Leakage ◽  
Secure Search ◽  
Boolean Expressions

Integrated ESD Robustness through Device Analysis of Ultra-Small Low Voltage Power MOSFETs

2014 ◽  
Author(s):  
Ian Kearney ◽  
Hank Sung
Keyword(s):  
New Product Development ◽  
Silicon Oxide ◽  
Low Voltage ◽  
Photon Emission ◽  
Electrical Characterization ◽  
Power Mosfets ◽  
Low Leakage ◽  
A Cell ◽  
Thermographic Analysis ◽  
Voltage Spike

Abstract Low voltage power MOSFETs often integrate voltage spike protection and gate oxide ESD protection. The basic concept of complete-static protection for the power MOSFETs is the prevention of static build-up where possible and the quick, reliable removal of existing charges. The power MOSFET gate is equivalent to a low voltage low leakage capacitor. The capacitor plates are formed primarily by the silicon gate and source metallization. The capacitor dielectric is the silicon oxide gate insulation. Smaller devices have less capacitance and require less charge per volt and are therefore more susceptible to ESD than larger MOSFETs. A FemtoFETTM is an ultra-small, low on-resistance MOSFET transistor for space-constrained handheld applications, such as smartphones and tablets. An ESD event, for example, between a fingertip and the communication-port connectors of a cell phone or tablet may cause permanent system damage. Through electrical characterization and global isolation by active photon emission, the authors identify and distinguish ESD failures. Thermographic analysis provided additional insight enabling further separation of ESD failmodes. This paper emphasizes the role of failure analysis in new product development from the create phase through to product ramp. Coupled with device electrical simulation, the analysis observations led to further design enhancement.

Optimization of sol-gel based fibre-optic cholinesterase biosensor for the determination of organophosphorus pesticides

2000 ◽  
Vol 42 (7-8) ◽  
pp. 283-290 ◽  
Author(s):  
H.-C. Tsai ◽  
R.-A. Doong
Keyword(s):  
Fiber Optic ◽  
Ph Value ◽  
Rapid Determination ◽  
Organophosphorus Pesticides ◽  
Sol Gel ◽  
Neutral Red ◽  
Fluorescent Indicators ◽  
Low Leakage ◽  
Fiber Optic System

A sol-gel based fiber-optic biosensor with acetylcholinesterase as the biorecognition element has been developed for the rapid determination of organophosphorus pesticides. Nine fluorescent indicators, acridine, acridine orange, neutral red, DAPI, rhodamine B, fluorescein, umbelliferone, FITC on celite and FITC-dextran, have been examined to optimize the fiber-optic system. Results showed that acridine and FITCs were sensitive to the change of pH value caused by the enzyme-substrate catalysis reaction. However, the sensitivity of acridine was 260 times lower than that of FITCs. Higher toxicity of acridine to acetylcholinesterase than FITC was also observed. Moreover, the high-molecular-weight FITC-dextran showed low leakage rate when immobilizing using sol-gel technology, showing that the FITC-dextran was a suitable pH sensitive fluorescent indicator for the OPPs biosensor. The response of the fiber-optic biosensor to the substrate, acetylcholine, was highly reproducible (RSD=3.5%). A good linearity of acetylcholine in the range from 0.5 to 20 mM was also obtained (R2=0.98). Furthermore, a 30% inhibition can be achieved in 30min when 152 ppb paraoxon was added into the system. The results show the possibility for real-time determination of organophosphorus pesticides by using the biosensor developed in this study.

High nonlinearity and low leakage current SnO2 varistor ceramics by co-doping with yttrium and tantalum

2021 ◽  
Vol 285 ◽  
pp. 129120
Author(s):  
Wenxin Liang ◽  
Hongfeng Zhao ◽  
Xiaoji Meng ◽  
Shaohua Fan ◽  
Qingyun Xie
Keyword(s):  
Leakage Current ◽  
Co Doping ◽  
High Nonlinearity ◽  
Low Leakage ◽  
Low Leakage Current

LOOKUP TABLE-BASED ADAPTIVE BODY BIASING OF MULTIPLE MACROS FOR PROCESS VARIATION COMPENSATION AND LOW LEAKAGE

2010 ◽  
Vol 19 (07) ◽  
pp. 1449-1464 ◽  
Author(s):  
BYUNGHEE CHOI ◽  
YOUNGSOO SHIN
Keyword(s):  
Supply Voltage ◽  
Process Variation ◽  
Power Saving ◽  
Lookup Table ◽  
Low Leakage ◽  
Fine Grain ◽  
Body Biasing ◽  
Block Level ◽  
Adaptive Body Bias ◽  
Body Bias

A reduced supply voltage must be accompanied by a reduced threshold voltage, which makes this approach to power saving susceptible to process variation in transistor parameters, as well as resulting in increased subthreshold leakage. While adaptive body biasing is efficient for both compensating process variation and suppressing leakage current, it suffers from a large overhead of control circuit. Most body biasing circuits target an entire chip, which causes excessive leakage of some blocks and misses the chance of fine grain control. We propose a new adaptive body biasing scheme, based on a lookup table for independent control of multiple functional blocks on a chip, which controls leakage and also compensates for process variation at the block level. An adaptive body bias is applied to blocks in active mode and a large reverse body bias is applied to blocks in standby mode. This is achieved by a central body bias controller, which has a low overhead in terms of area, delay, and power consumption. The problem of optimizing the required set of bias voltages is formulated and solved. A design methodology for semicustom design using standard-cell elements is developed and verified with benchmark circuits.

Constrained Petri Nets. Part II: Generalizations and extensions

1983 ◽  
Vol 6 (3-4) ◽  
pp. 333-374
Author(s):  
H.J.M. Goeman ◽  
L.P.J. Groenewegen ◽  
H.C.M. Kleijn ◽  
G. Rozenberg
Keyword(s):  
Petri Nets ◽  
Petri Net ◽  
Theoretical Framework ◽  
General Constraints ◽  
Context Free ◽  
Boolean Expressions

This paper continues the investigation froll1 [Goeman et al.] concerning the use of sets of places of a Petri net as additional (to input places) constraints for granting concession. Now interpretations of more general constraints are considered and expressed as Boolean expressions. This gives rise to various classes of constrained Petri nets. These are compared in the language theoretical framework introduced in [Goeman et al.]. An upperbound for the language defining power is found in the class of context-free programmed languages.

Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm

2021 ◽  
Vol 85 ◽  
pp. 104281
Author(s):  
Monica Gupta ◽  
Kirti Gupta ◽  
Neeta Pandey
Keyword(s):  
Comparative Analysis ◽  
Low Leakage ◽  
Design Techniques
Sign in / Sign up

Export Citation Format

Share Document