Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating

The scaling of CMOS technology has continued due to ever increasing demand of greater performance with low power consumption. This demand has grown further by the portable and battery operated devices market. To meet the challenge of greater energy efficiency and performance, a number of power optimization techniques at processor and system components level are proposed by the research community such as clock gating, operand isolation, memory splitting, power gating, dynamic voltage and frequency scaling, etc. This chapter reviews advancements in the dynamic power optimization techniques like clock gating and power gating. This chapter also reviews some architectures and optimization techniques that have been developed for greater power reduction without any significant performance degradation or area cost.

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Low-Power FSM Synthesis Based on Automated Power and Clock Gating Technique

Journal of Circuits System and Computers ◽

10.1142/s0218126619200032 ◽

2019 ◽

Vol 28 (05) ◽

pp. 1920003 ◽

Cited By ~ 1

Author(s):

Abhishek Nag ◽

Subhajit Das ◽

Sambhu Nath Pradhan

Keyword(s):

Power Dissipation ◽

The State ◽

Digital Design ◽

Total Power ◽

Clock Signal ◽

Power Gating ◽

Clock Gating ◽

Control Logic ◽

Area Overhead ◽

Finite State

This work introduces a concept of integrating clock gating and power gating in finite state machines (FSMs) to reduce the overall power dissipation. The theory of the proposed power gating technique is to shut down the power supply during periods of inactivity of the FSM. The inactive period is identified by the occurrence of self-loops within the FSM or an unchanged FSM output between successive clock pulses. Clock gating on the other hand disables the clock signal to the sequential blocks of the FSM during this inactive/idle periods. The proposed approach introduces the concept of gating into both the state logic (DGS) and output logic (DGO) in FSM separately and can be implemented in general to all FSMs. The control logic for gating automatically extracts information from the state description of the FSM. An efficient method of partitioning of the FSM is also proposed in this paper to effectively implement the gating techniques. The dual gating approach has been introduced in 10 standard benchmark FSM circuits for DGS technique and later extended to four FSMs for implementing “DGS[Formula: see text][Formula: see text][Formula: see text]DGO.” Then the circuits are simulated and synthesized in CADENCE analog and digital design tools. Simulation results show a maximum power reduction of 62.17% in DGS technique and 73% total power savings after implementing “DGS[Formula: see text][Formula: see text][Formula: see text]DGO.” The average area overhead in DGS technique is 12.9% whereas in DGS[Formula: see text][Formula: see text][Formula: see text]DGO, the area increases by 22.6%. The area overhead and the delay tend to reduce as the size of the FSM increases.

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Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating Integration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2012.2212732 ◽

2013 ◽

Vol 21 (8) ◽

pp. 1540-1544 ◽

Cited By ~ 6

Author(s):

Li Li ◽

Ken Choi ◽

Haiqing Nan

Keyword(s):

Power Gating ◽

Clock Gating ◽

Fine Grained ◽

Run Time

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