ANTS ROAD: A New Tool for SQLite Data Recovery on Android Devices

2013 ◽  
pp. 253-263 ◽  
Author(s):  
Lamine M. Aouad ◽  
Tahar M. Kechadi ◽  
Roberto Di Russo
Keyword(s):  
Data Recovery

scholarly journals A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 780
Author(s):  
Matteo D’Addato ◽  
Alessia M. Elgani ◽  
Luca Perilli ◽  
Eleonora Franchi Scarselli ◽  
Antonio Gnudi ◽  
...  
Keyword(s):  
Data Streams ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Rf Power ◽  
Input Matching ◽  
Analog Front End ◽  
Frequency Mismatch ◽  
Free Running ◽  
Frequency Calibration ◽  
Total Sensitivity

This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to Nm = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10−3 missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the Nm ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups.

scholarly journals Equalizer State Caching for Fast Data Recovery in Optically-Switched Data Center Networks

2021 ◽  
pp. 1-1
Author(s):  
Zhouyi Hu ◽  
Zichuan Zhou ◽  
Chun Kit Calvin Chan ◽  
Zhixin Liu
Keyword(s):  
Data Center ◽  
Data Recovery ◽  
Data Center Networks

Design of high-speed burst mode clock and data recovery IC for passive optical network

2005 ◽  
Author(s):  
Minhui Yan ◽  
Xiaobin Hong ◽  
Wei-Ping Huang ◽  
Jin Hong
Keyword(s):  
High Speed ◽  
Optical Network ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Passive Optical Network ◽  
Burst Mode

A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-${\rm \mu}\hbox{m}$ CMOS Technology

2009 ◽  
Vol 56 (1) ◽  
pp. 6-10 ◽  
Author(s):  
Young-Suk Seo ◽  
Jang-Woo Lee ◽  
Hong-Jung Kim ◽  
Changsik Yoo ◽  
Jae-Jin Lee ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Linear Phase
Sign in / Sign up

Export Citation Format

Share Document