Redesigned and Reinforced Low-Power Data Encryption Standard Using Hash Codes for High-Speed and High-Secure Applications

2017 ◽  
pp. 3-16
Author(s):  
Thrived Dharbhashayanam ◽  
K. Manjunatha Chari ◽  
Pramod Dharbhashayanam
Keyword(s):  
Low Power ◽  
High Speed ◽  
Data Encryption ◽  
Data Encryption Standard ◽  
Hash Codes

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

scholarly journals VLSI Design flow for Secure Integrated Circuits based on DES, TDES, AES and Blowfish Algorithms and their performance

2018 ◽  
Vol 7 (2.16) ◽  
pp. 94
Author(s):  
Kumara Swamy Varkuti ◽  
Prabhu Benakop
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Vlsi Design ◽  
Data Encryption ◽  
Vital Role ◽  
Design Flow ◽  
Information Communication ◽  
Verilog Hdl ◽  
Data Encryption Standard ◽  
Memory Utilization

Information Communication Technology (ICT) and Information Security (IS) are playing vital role in the present day communications. Information is prone to side channel attacks at software level where as it is very difficult to hack the information at hardware level.  Security is the major concern in the paperless communication and cashless online transactions. This paper aims to implement the most secured Improved Modified Blowfish Algorithm (IMBFA) by incorporating cell substitution using Wave Dynamic Differential Logic (WDDL) and interconnect decomposition  in the VLSI Design flow to not to allow the hacker to estimate or predict the key. Proposed IMBFA which can result in high speed, high throughput and effective memory utilization compared to Data Encryption Standard (DES), Triple Data Encryption Standard (TDES), Advanced Encryption Standard (AES) and Blowfish (BF). In this research paper, IMBFA yielded minimum delay as 71.067 ns, frequency of the design as 14.07 MHz, memory utilization as 62.481MB and throughput is 900Mbps compared to AES, TDES and DES algorithms. It is simulated using ModelSim, Synthesized using Leonardo Spectrum and implemented using Verilog HDL. 

HIGH SPEED AND LOW POWER 4*4 ARRAY MULTIPLIER DESIGN

2019 ◽  
Vol 7 (1) ◽  
pp. 24
Author(s):  
N. SURESH ◽  
K. S. SHAJI ◽  
KISHORE REDDY M. CHAITANYA ◽  
◽  
◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Array Multiplier

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

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