Topology Structure Design of Fish-Based Propulsive Mechanisms

2021 ◽  
pp. 1055-1065
Author(s):  
Gaikwad Pankaj Manik ◽  
Pankaj Dorlikar
Keyword(s):  
Structure Design ◽  
Topology Structure

Topology Analyses and Position Solution Based on Asymmetric and Fewer DOF Parallel Robots

2011 ◽  
Vol 308-310 ◽  
pp. 1252-1257
Author(s):  
Ping An Liu ◽  
Xiao Heng Shi
Keyword(s):  
Degrees Of Freedom ◽  
Analytical Approach ◽  
Structure Design ◽  
Parallel Robots ◽  
Forward Kinematics ◽  
Topology Structure ◽  
Constrained Equations ◽  
Position Solution

By using the theory and method of topology structure design of parallel robotic mechanisms, the degrees of freedom (DOF) is analyzed based on 4-DOF(3T1R) asymmetric parallel robots in this paper. Then, the inverse and forward kinematics of the manipulator are calculated through establishment of constrained equations with analytical approach.

Influence of unbalanced magnetic force on shaft deflection in permanent magnet synchronous motor with fractional slot concentrated windings

2020 ◽  
Vol 64 (1-4) ◽  
pp. 1461-1468
Author(s):  
Ting Dong ◽  
Juyan Huang ◽  
Bing Peng ◽  
Ling Jian
Keyword(s):  
Permanent Magnet ◽  
Magnetic Force ◽  
Permanent Magnet Synchronous Motor ◽  
Operational Reliability ◽  
Topology Structure ◽  
Permanent Magnet Synchronous Motors ◽  
Synchronous Motors ◽  
Shaft Deflection ◽  
Large Length ◽  
Fractional Slot

The calculation accuracy of unbalanced magnetic forces (UMF) is very important to the design of rotor length, because it will effect the shaft deflection. But in some permanent magnet synchronous motors (PMSMs) with fractional slot concentrated windings (FSCW), the UMF caused by asymmetrical stator topology structure is not considered in the existing deflection calculation, which is very fatal for the operational reliability, especially for the PMSMs with the large length-diameter ratio, such as submersible PMSMs. Therefore, the part of UMF in the asymmetrical stator topology structure PMSMs caused by the choice of pole-slot combinations is analysized in this paper, and a more accurate rotor deflection calculation method is also proposed.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

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