A Low Leakage with Enhanced Write Margin 10T SRAM Cell for IoT Applications

2021 ◽  
pp. 201-211
Author(s):  
Vaishali Yadav ◽  
V. K. Tomar
Keyword(s):  
Iot Applications ◽  
Low Leakage ◽  
Sram Cell

scholarly journals Low Leakage SRAM Cell with Improved Stability for IoT Applications

2020 ◽  
Vol 171 ◽  
pp. 1469-1478
Author(s):  
Chusen Duari ◽  
Shilpi Birla
Keyword(s):  
Iot Applications ◽  
Low Leakage ◽  
Sram Cell ◽  
Improved Stability

A Low Leakage Variation-Aware 10T SRAM Cell for IoT Applications

2021 ◽  
Author(s):  
Pushpa Raikwal ◽  
Ambika Prasad Shah ◽  
Vaibhav Neema
Keyword(s):  
Iot Applications ◽  
Low Leakage ◽  
Sram Cell

scholarly journals Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1718
Author(s):  
Neha Gupta ◽  
Ambika Prasad Shah ◽  
Sajid Khan ◽  
Santosh Kumar Vishvakarma ◽  
Michael Waltl ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Leakage Power ◽  
Functional Improvement ◽  
Scaling Technique ◽  
Iot Applications ◽  
Sram Cell ◽  
Improved Stability ◽  
Supply Voltage Scaling ◽  
Power Delay Product

This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage.

A 12T MT-CMOS low power and low leakage SRAM cell

2017 ◽  
Vol 9 (3) ◽  
pp. 307 ◽  
Author(s):  
Prashant Upadhyay ◽  
Rajib Kar ◽  
Durbadal Mandal ◽  
Sakti Prasad Ghoshal
Keyword(s):  
Low Power ◽  
Low Leakage ◽  
Sram Cell

Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories

2019 ◽  
Vol 108 (4) ◽  
pp. 2311-2339 ◽  
Author(s):  
K. Gavaskar ◽  
U. S. Ragupathy ◽  
V. Malini
Keyword(s):  
High Speed ◽  
Low Leakage ◽  
Sram Cell ◽  
Embedded Memories

Design of a novel CMOS/MTJ-based multibit SRAM cell with low store energy for IoT applications

2019 ◽  
Vol 107 (6) ◽  
pp. 899-914
Author(s):  
Kanika Monga ◽  
Nitin Chaturvedi ◽  
S. Gurunarayanan
Keyword(s):  
Iot Applications ◽  
Sram Cell

A single-ended low leakage and low voltage 10T SRAM cell with high yield

2020 ◽  
Vol 105 (2) ◽  
pp. 263-274
Author(s):  
Nima Eslami ◽  
Behzad Ebrahimi ◽  
Erfan Shakouri ◽  
Deniz Najafi
Keyword(s):  
Low Voltage ◽  
High Yield ◽  
Low Leakage ◽  
Sram Cell
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