A 12T MT-CMOS low power and low leakage SRAM cell

2017 ◽  
Vol 9 (3) ◽  
pp. 307 ◽  
Author(s):  
Prashant Upadhyay ◽  
Rajib Kar ◽  
Durbadal Mandal ◽  
Sakti Prasad Ghoshal
Keyword(s):  
Low Power ◽  
Low Leakage ◽  
Sram Cell

A 12T MT-CMOS low power and low leakage SRAM cell

2017 ◽  
Vol 9 (3) ◽  
pp. 307
Author(s):  
Durbadal Mandal ◽  
Sakti Prasad Ghoshal ◽  
Rajib Kar ◽  
Prashant Upadhyay
Keyword(s):  
Low Power ◽  
Low Leakage ◽  
Sram Cell

scholarly journals Low Power, High speed, Low leakage Floating Gate SRAM Cell using LECTOR Technique

2016 ◽  
Vol 9 (45) ◽  
Author(s):  
Kanan Bala Ray ◽  
Sushanta K. Mandal ◽  
B. Shivalal Patro
Keyword(s):  
Low Power ◽  
High Speed ◽  
Floating Gate ◽  
Low Leakage ◽  
Sram Cell

Design of Low Leakage 9T SRAM Cell with -Low Power Devices

2021 ◽  
pp. 2250027
Author(s):  
Harekrishna Kumar ◽  
V.K Tomar
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Schmitt Trigger ◽  
Leakage Power ◽  
Access Time ◽  
Threshold Region ◽  
Large Area ◽  
Transmission Gate ◽  
Low Leakage ◽  
Sram Cell

In this paper, a 9T SRAM cell with low power (LP9T) and improved performance has been proposed. This cell is free from half-select issue and works with single-ended read and differential write operation in the sub-threshold region. To evaluate the relative performance, the obtained characteristics of LP9T SRAM cell are compared with other state-of-the-art designs at 45-nm technology node. The read and write power dissipation of LP9T SRAM cell is reduced by [Formula: see text] and [Formula: see text] as compared to Conv.6T SRAM cell. In proposed cell, leakage power is reduced by [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text] and [Formula: see text] as compared to conventional 6T (Conv.6T), low power (LP8T), transmission gate 8T(TG8T), transmission gate 9T (TG9T), Schmitt trigger 9T (ST9T), and positive feedback control 10T (PFC10T) SRAM cells. This reduction in leakage power is attributed to stacking effect. LP9T SRAM cell also exhibits significant improvement in read/write access time as compared to all considered cells. Also, the read and write energy of proposed cell is lowest among all considered cells. The LP9T SRAM cell has [Formula: see text] and [Formula: see text] higher read and write stability as compared to Conv.6T SRAM cell. Proposed SRAM cell has the highest value of ON to OFF current ratio ([Formula: see text]) which signifies the highest bit-cell density among all considered cells. The LP9T SRAM cell occupies [Formula: see text] large area as compared to Conv.6T SRAM cell. The overall quality of SRAM cell is calculated through the electrical quality metric (EQM). It is observed that LP9T SRAM cell has the highest value of EQM in comparison to considered cells at 0.3[Formula: see text]V supply voltage.

Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell

2019 ◽  
pp. 643-654 ◽  
Author(s):  
Neha Gupta ◽  
Tanisha Gupta ◽  
Sajid Khan ◽  
Abhinav Vishwakarma ◽  
Santosh Kumar Vishvakarma
Keyword(s):  
Low Power ◽  
Ultra Low Power ◽  
Low Leakage ◽  
Sram Cell

scholarly journals Low leakage SRAM cell for ULP applications

2018 ◽  
Vol 7 (4) ◽  
pp. 2521
Author(s):  
Tripti Tripathi ◽  
D. S. Chauhan ◽  
S. K. Singh
Keyword(s):  
Low Power ◽  
Electronic Devices ◽  
Leakage Power ◽  
Power Devices ◽  
Low Leakage ◽  
Sram Cell ◽  
Design Cycle ◽  
Mode Of Operation ◽  
Power Leakage ◽  
Standby Mode

Leakage power is becoming a major concern in battery operated and hand held devices. With the ever reducing size of electronic devices and the use of memory in most of them, the need for low power devices is vastly increasing. These devices are either in active or standby mode of operation. Leakage power in standby mode of operation is of major concern and various methods to minimize it have been proposed at various stages of design cycle. This paper proposes fingering technique that can be used in 6T SRAM cell to reduce leakage power. Leakage power is calculated for 6T SRAM cell designed using two fingers in access transistors and on comparison with conventional 6T SRAM cell, significant reduction in leakage current is obtained. The layout has been designed in UMC 55nm technology using Cadence Virtuoso tool and it has been shown that the leakage power and delay can be reduced.  

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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