A single-ended low leakage and low voltage 10T SRAM cell with high yield

2020 ◽  
Vol 105 (2) ◽  
pp. 263-274
Author(s):  
Nima Eslami ◽  
Behzad Ebrahimi ◽  
Erfan Shakouri ◽  
Deniz Najafi
Keyword(s):  
Low Voltage ◽  
High Yield ◽  
Low Leakage ◽  
Sram Cell

High-yield design of high-density SRAM for low-voltage and low-leakage operations

2017 ◽  
Author(s):  
Kedar Janardan Dhori ◽  
Hitesh Chawla ◽  
Ashish Kumar ◽  
Prashant Pandey ◽  
Promod Kumar ◽  
...  
Keyword(s):  
Low Voltage ◽  
High Density ◽  
High Yield ◽  
Low Leakage

scholarly journals Low‐Voltage, Printed, All‐Polymer Integrated Circuits Employing a Low‐Leakage and High‐Yield Polymer Dielectric

2018 ◽  
Vol 4 (12) ◽  
pp. 1800340 ◽  
Author(s):  
Elena Stucchi ◽  
Giorgio Dell'Erba ◽  
Paolo Colpani ◽  
Yun‐Hi Kim ◽  
Mario Caironi
Keyword(s):  
Integrated Circuits ◽  
Low Voltage ◽  
High Yield ◽  
Polymer Dielectric ◽  
Low Leakage

Integrated ESD Robustness through Device Analysis of Ultra-Small Low Voltage Power MOSFETs

2014 ◽  
Author(s):  
Ian Kearney ◽  
Hank Sung
Keyword(s):  
New Product Development ◽  
Silicon Oxide ◽  
Low Voltage ◽  
Photon Emission ◽  
Electrical Characterization ◽  
Power Mosfets ◽  
Low Leakage ◽  
A Cell ◽  
Thermographic Analysis ◽  
Voltage Spike

Abstract Low voltage power MOSFETs often integrate voltage spike protection and gate oxide ESD protection. The basic concept of complete-static protection for the power MOSFETs is the prevention of static build-up where possible and the quick, reliable removal of existing charges. The power MOSFET gate is equivalent to a low voltage low leakage capacitor. The capacitor plates are formed primarily by the silicon gate and source metallization. The capacitor dielectric is the silicon oxide gate insulation. Smaller devices have less capacitance and require less charge per volt and are therefore more susceptible to ESD than larger MOSFETs. A FemtoFETTM is an ultra-small, low on-resistance MOSFET transistor for space-constrained handheld applications, such as smartphones and tablets. An ESD event, for example, between a fingertip and the communication-port connectors of a cell phone or tablet may cause permanent system damage. Through electrical characterization and global isolation by active photon emission, the authors identify and distinguish ESD failures. Thermographic analysis provided additional insight enabling further separation of ESD failmodes. This paper emphasizes the role of failure analysis in new product development from the create phase through to product ramp. Coupled with device electrical simulation, the analysis observations led to further design enhancement.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

An optimized process for fabrication of SrBi2Ta2O9 thin films using a novel chemical solution deposition technique

1999 ◽  
Vol 14 (11) ◽  
pp. 4395-4401 ◽  
Author(s):  
Seung-Hyun Kim ◽  
D. J. Kim ◽  
K. M. Lee ◽  
M. Park ◽  
A. I. Kingon ◽  
...  
Keyword(s):  
Thin Films ◽  
Chemical Solution Deposition ◽  
Low Voltage ◽  
Ferroelectric Properties ◽  
Chemical Solution ◽  
Solution Deposition ◽  
Chemical Solution Deposition Method ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Voltage Saturation

Ferroelectric SrBi2Ta2O9 (SBT) thin films on Pt/ZrO2/SiO2/Si were successfully prepared by using an alkanolamine-modified chemical solution deposition method. It was observed that alkanolamine provided stability to the SBT solution by retarding the hydrolysis and condensation rates. The crystallinity and the microstructure of the SBT thin films improved with increasing annealing temperature and were strongly correlated with the ferroelectric properties of the SBT thin films. The films annealed at 800 °C exhibited low leakage current density, low voltage saturation, high remanent polarization, and good fatigue characteristics at least up to 1010 switching cycles, indicating favorable behavior for memory applications.

A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

2013 ◽  
Vol 373-375 ◽  
pp. 1607-1611
Author(s):  
Hong Gang Zhou ◽  
Shou Biao Tan ◽  
Qiang Song ◽  
Chun Yu Peng
Keyword(s):  
Error Correction ◽  
Low Voltage ◽  
Cmos Technology ◽  
Soft Error ◽  
Error Correction Codes ◽  
Cell Design ◽  
Low Voltage Operation ◽  
Sram Cell ◽  
Simulation Results ◽  
Nanometer Regime

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

2015 ◽  
Vol 43 (12) ◽  
pp. 2011-2024 ◽  
Author(s):  
Behzad Ebrahimi ◽  
Reza Asadpour ◽  
Ali Afzali-Kusha ◽  
Massoud Pedram
Keyword(s):  
High Yield ◽  
Cell Design ◽  
Sram Cell ◽  
Supply Voltages

A 12T MT-CMOS low power and low leakage SRAM cell

2017 ◽  
Vol 9 (3) ◽  
pp. 307 ◽  
Author(s):  
Prashant Upadhyay ◽  
Rajib Kar ◽  
Durbadal Mandal ◽  
Sakti Prasad Ghoshal
Keyword(s):  
Low Power ◽  
Low Leakage ◽  
Sram Cell
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